registers.hh revision 13592:b8972ccebd63 
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2016 RISC-V Foundation
16 * Copyright (c) 2016 The University of Virginia
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Andreas Hansson
43 *          Sven Karlsson
44 *          Alec Roelke
45 */
46
47#ifndef __ARCH_RISCV_REGISTERS_HH__
48#define __ARCH_RISCV_REGISTERS_HH__
49
50#include <map>
51#include <string>
52#include <vector>
53
54#include "arch/generic/types.hh"
55#include "arch/generic/vec_reg.hh"
56#include "arch/isa_traits.hh"
57#include "arch/riscv/generated/max_inst_regs.hh"
58#include "base/types.hh"
59
60namespace RiscvISA {
61
62using RiscvISAInst::MaxInstSrcRegs;
63using RiscvISAInst::MaxInstDestRegs;
64const int MaxMiscDestRegs = 1;
65
66typedef RegVal IntReg;
67typedef RegVal FloatRegBits;
68typedef uint8_t CCReg; // Not applicable to Riscv
69typedef RegVal MiscReg;
70
71// dummy typedefs since we don't have vector regs
72const unsigned NumVecElemPerVecReg = 2;
73using VecElem = uint32_t;
74using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
75using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
76using VecRegContainer = VecReg::Container;
77
78const int NumIntArchRegs = 32;
79const int NumMicroIntRegs = 1;
80const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
81const int NumFloatRegs = 32;
82// This has to be one to prevent warnings that are treated as errors
83const unsigned NumVecRegs = 1;
84const int NumCCRegs = 0;
85
86// Semantically meaningful register indices
87const int ZeroReg = 0;
88const int ReturnAddrReg = 1;
89const int StackPointerReg = 2;
90const int GlobalPointerReg = 3;
91const int ThreadPointerReg = 4;
92const int FramePointerReg = 8;
93const int ReturnValueReg = 10;
94const std::vector<int> ReturnValueRegs = {10, 11};
95const std::vector<int> ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
96const int AMOTempReg = 32;
97
98const int SyscallPseudoReturnReg = 10;
99const std::vector<int> SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
100const int SyscallNumReg = 17;
101
102const std::vector<std::string> IntRegNames = {
103    "zero", "ra", "sp", "gp",
104    "tp", "t0", "t1", "t2",
105    "s0", "s1", "a0", "a1",
106    "a2", "a3", "a4", "a5",
107    "a6", "a7", "s2", "s3",
108    "s4", "s5", "s6", "s7",
109    "s8", "s9", "s10", "s11",
110    "t3", "t4", "t5", "t6"
111};
112const std::vector<std::string> FloatRegNames = {
113    "ft0", "ft1", "ft2", "ft3",
114    "ft4", "ft5", "ft6", "ft7",
115    "fs0", "fs1", "fa0", "fa1",
116    "fa2", "fa3", "fa4", "fa5",
117    "fa6", "fa7", "fs2", "fs3",
118    "fs4", "fs5", "fs6", "fs7",
119    "fs8", "fs9", "fs10", "fs11",
120    "ft8", "ft9", "ft10", "ft11"
121};
122
123enum MiscRegIndex {
124    MISCREG_PRV = 0,
125    MISCREG_ISA,
126    MISCREG_VENDORID,
127    MISCREG_ARCHID,
128    MISCREG_IMPID,
129    MISCREG_HARTID,
130    MISCREG_STATUS,
131    MISCREG_IP,
132    MISCREG_IE,
133    MISCREG_CYCLE,
134    MISCREG_TIME,
135    MISCREG_INSTRET,
136    MISCREG_HPMCOUNTER03,
137    MISCREG_HPMCOUNTER04,
138    MISCREG_HPMCOUNTER05,
139    MISCREG_HPMCOUNTER06,
140    MISCREG_HPMCOUNTER07,
141    MISCREG_HPMCOUNTER08,
142    MISCREG_HPMCOUNTER09,
143    MISCREG_HPMCOUNTER10,
144    MISCREG_HPMCOUNTER11,
145    MISCREG_HPMCOUNTER12,
146    MISCREG_HPMCOUNTER13,
147    MISCREG_HPMCOUNTER14,
148    MISCREG_HPMCOUNTER15,
149    MISCREG_HPMCOUNTER16,
150    MISCREG_HPMCOUNTER17,
151    MISCREG_HPMCOUNTER18,
152    MISCREG_HPMCOUNTER19,
153    MISCREG_HPMCOUNTER20,
154    MISCREG_HPMCOUNTER21,
155    MISCREG_HPMCOUNTER22,
156    MISCREG_HPMCOUNTER23,
157    MISCREG_HPMCOUNTER24,
158    MISCREG_HPMCOUNTER25,
159    MISCREG_HPMCOUNTER26,
160    MISCREG_HPMCOUNTER27,
161    MISCREG_HPMCOUNTER28,
162    MISCREG_HPMCOUNTER29,
163    MISCREG_HPMCOUNTER30,
164    MISCREG_HPMCOUNTER31,
165    MISCREG_HPMEVENT03,
166    MISCREG_HPMEVENT04,
167    MISCREG_HPMEVENT05,
168    MISCREG_HPMEVENT06,
169    MISCREG_HPMEVENT07,
170    MISCREG_HPMEVENT08,
171    MISCREG_HPMEVENT09,
172    MISCREG_HPMEVENT10,
173    MISCREG_HPMEVENT11,
174    MISCREG_HPMEVENT12,
175    MISCREG_HPMEVENT13,
176    MISCREG_HPMEVENT14,
177    MISCREG_HPMEVENT15,
178    MISCREG_HPMEVENT16,
179    MISCREG_HPMEVENT17,
180    MISCREG_HPMEVENT18,
181    MISCREG_HPMEVENT19,
182    MISCREG_HPMEVENT20,
183    MISCREG_HPMEVENT21,
184    MISCREG_HPMEVENT22,
185    MISCREG_HPMEVENT23,
186    MISCREG_HPMEVENT24,
187    MISCREG_HPMEVENT25,
188    MISCREG_HPMEVENT26,
189    MISCREG_HPMEVENT27,
190    MISCREG_HPMEVENT28,
191    MISCREG_HPMEVENT29,
192    MISCREG_HPMEVENT30,
193    MISCREG_HPMEVENT31,
194    MISCREG_TSELECT,
195    MISCREG_TDATA1,
196    MISCREG_TDATA2,
197    MISCREG_TDATA3,
198    MISCREG_DCSR,
199    MISCREG_DPC,
200    MISCREG_DSCRATCH,
201
202    MISCREG_MEDELEG,
203    MISCREG_MIDELEG,
204    MISCREG_MTVEC,
205    MISCREG_MCOUNTEREN,
206    MISCREG_MSCRATCH,
207    MISCREG_MEPC,
208    MISCREG_MCAUSE,
209    MISCREG_MTVAL,
210    MISCREG_PMPCFG0,
211    // pmpcfg1 rv32 only
212    MISCREG_PMPCFG2,
213    // pmpcfg3 rv32 only
214    MISCREG_PMPADDR00,
215    MISCREG_PMPADDR01,
216    MISCREG_PMPADDR02,
217    MISCREG_PMPADDR03,
218    MISCREG_PMPADDR04,
219    MISCREG_PMPADDR05,
220    MISCREG_PMPADDR06,
221    MISCREG_PMPADDR07,
222    MISCREG_PMPADDR08,
223    MISCREG_PMPADDR09,
224    MISCREG_PMPADDR10,
225    MISCREG_PMPADDR11,
226    MISCREG_PMPADDR12,
227    MISCREG_PMPADDR13,
228    MISCREG_PMPADDR14,
229    MISCREG_PMPADDR15,
230
231    MISCREG_SEDELEG,
232    MISCREG_SIDELEG,
233    MISCREG_STVEC,
234    MISCREG_SCOUNTEREN,
235    MISCREG_SSCRATCH,
236    MISCREG_SEPC,
237    MISCREG_SCAUSE,
238    MISCREG_STVAL,
239    MISCREG_SATP,
240
241    MISCREG_UTVEC,
242    MISCREG_USCRATCH,
243    MISCREG_UEPC,
244    MISCREG_UCAUSE,
245    MISCREG_UTVAL,
246    MISCREG_FFLAGS,
247    MISCREG_FRM,
248
249    NUM_MISCREGS
250};
251const int NumMiscRegs = NUM_MISCREGS;
252
253enum CSRIndex {
254    CSR_USTATUS = 0x000,
255    CSR_UIE = 0x004,
256    CSR_UTVEC = 0x005,
257    CSR_USCRATCH = 0x040,
258    CSR_UEPC = 0x041,
259    CSR_UCAUSE = 0x042,
260    CSR_UTVAL = 0x043,
261    CSR_UIP = 0x044,
262    CSR_FFLAGS = 0x001,
263    CSR_FRM = 0x002,
264    CSR_FCSR = 0x003,
265    CSR_CYCLE = 0xC00,
266    CSR_TIME = 0xC01,
267    CSR_INSTRET = 0xC02,
268    CSR_HPMCOUNTER03 = 0xC03,
269    CSR_HPMCOUNTER04 = 0xC04,
270    CSR_HPMCOUNTER05 = 0xC05,
271    CSR_HPMCOUNTER06 = 0xC06,
272    CSR_HPMCOUNTER07 = 0xC07,
273    CSR_HPMCOUNTER08 = 0xC08,
274    CSR_HPMCOUNTER09 = 0xC09,
275    CSR_HPMCOUNTER10 = 0xC0A,
276    CSR_HPMCOUNTER11 = 0xC0B,
277    CSR_HPMCOUNTER12 = 0xC0C,
278    CSR_HPMCOUNTER13 = 0xC0D,
279    CSR_HPMCOUNTER14 = 0xC0E,
280    CSR_HPMCOUNTER15 = 0xC0F,
281    CSR_HPMCOUNTER16 = 0xC10,
282    CSR_HPMCOUNTER17 = 0xC11,
283    CSR_HPMCOUNTER18 = 0xC12,
284    CSR_HPMCOUNTER19 = 0xC13,
285    CSR_HPMCOUNTER20 = 0xC14,
286    CSR_HPMCOUNTER21 = 0xC15,
287    CSR_HPMCOUNTER22 = 0xC16,
288    CSR_HPMCOUNTER23 = 0xC17,
289    CSR_HPMCOUNTER24 = 0xC18,
290    CSR_HPMCOUNTER25 = 0xC19,
291    CSR_HPMCOUNTER26 = 0xC1A,
292    CSR_HPMCOUNTER27 = 0xC1B,
293    CSR_HPMCOUNTER28 = 0xC1C,
294    CSR_HPMCOUNTER29 = 0xC1D,
295    CSR_HPMCOUNTER30 = 0xC1E,
296    CSR_HPMCOUNTER31 = 0xC1F,
297    // HPMCOUNTERH rv32 only
298
299    CSR_SSTATUS = 0x100,
300    CSR_SEDELEG = 0x102,
301    CSR_SIDELEG = 0x103,
302    CSR_SIE = 0x104,
303    CSR_STVEC = 0x105,
304    CSR_SSCRATCH = 0x140,
305    CSR_SEPC = 0x141,
306    CSR_SCAUSE = 0x142,
307    CSR_STVAL = 0x143,
308    CSR_SIP = 0x144,
309    CSR_SATP = 0x180,
310
311    CSR_MVENDORID = 0xF11,
312    CSR_MARCHID = 0xF12,
313    CSR_MIMPID = 0xF13,
314    CSR_MHARTID = 0xF14,
315    CSR_MSTATUS = 0x300,
316    CSR_MISA = 0x301,
317    CSR_MEDELEG = 0x302,
318    CSR_MIDELEG = 0x303,
319    CSR_MIE = 0x304,
320    CSR_MTVEC = 0x305,
321    CSR_MSCRATCH = 0x340,
322    CSR_MEPC = 0x341,
323    CSR_MCAUSE = 0x342,
324    CSR_MTVAL = 0x343,
325    CSR_MIP = 0x344,
326    CSR_PMPCFG0 = 0x3A0,
327    // pmpcfg1 rv32 only
328    CSR_PMPCFG2 = 0x3A2,
329    // pmpcfg3 rv32 only
330    CSR_PMPADDR00 = 0x3B0,
331    CSR_PMPADDR01 = 0x3B1,
332    CSR_PMPADDR02 = 0x3B2,
333    CSR_PMPADDR03 = 0x3B3,
334    CSR_PMPADDR04 = 0x3B4,
335    CSR_PMPADDR05 = 0x3B5,
336    CSR_PMPADDR06 = 0x3B6,
337    CSR_PMPADDR07 = 0x3B7,
338    CSR_PMPADDR08 = 0x3B8,
339    CSR_PMPADDR09 = 0x3B9,
340    CSR_PMPADDR10 = 0x3BA,
341    CSR_PMPADDR11 = 0x3BB,
342    CSR_PMPADDR12 = 0x3BC,
343    CSR_PMPADDR13 = 0x3BD,
344    CSR_PMPADDR14 = 0x3BE,
345    CSR_PMPADDR15 = 0x3BF,
346    CSR_MCYCLE = 0xB00,
347    CSR_MINSTRET = 0xB02,
348    CSR_MHPMCOUNTER03 = 0xC03,
349    CSR_MHPMCOUNTER04 = 0xC04,
350    CSR_MHPMCOUNTER05 = 0xC05,
351    CSR_MHPMCOUNTER06 = 0xC06,
352    CSR_MHPMCOUNTER07 = 0xC07,
353    CSR_MHPMCOUNTER08 = 0xC08,
354    CSR_MHPMCOUNTER09 = 0xC09,
355    CSR_MHPMCOUNTER10 = 0xC0A,
356    CSR_MHPMCOUNTER11 = 0xC0B,
357    CSR_MHPMCOUNTER12 = 0xC0C,
358    CSR_MHPMCOUNTER13 = 0xC0D,
359    CSR_MHPMCOUNTER14 = 0xC0E,
360    CSR_MHPMCOUNTER15 = 0xC0F,
361    CSR_MHPMCOUNTER16 = 0xC10,
362    CSR_MHPMCOUNTER17 = 0xC11,
363    CSR_MHPMCOUNTER18 = 0xC12,
364    CSR_MHPMCOUNTER19 = 0xC13,
365    CSR_MHPMCOUNTER20 = 0xC14,
366    CSR_MHPMCOUNTER21 = 0xC15,
367    CSR_MHPMCOUNTER22 = 0xC16,
368    CSR_MHPMCOUNTER23 = 0xC17,
369    CSR_MHPMCOUNTER24 = 0xC18,
370    CSR_MHPMCOUNTER25 = 0xC19,
371    CSR_MHPMCOUNTER26 = 0xC1A,
372    CSR_MHPMCOUNTER27 = 0xC1B,
373    CSR_MHPMCOUNTER28 = 0xC1C,
374    CSR_MHPMCOUNTER29 = 0xC1D,
375    CSR_MHPMCOUNTER30 = 0xC1E,
376    CSR_MHPMCOUNTER31 = 0xC1F,
377    // MHPMCOUNTERH rv32 only
378    CSR_MHPMEVENT03 = 0x323,
379    CSR_MHPMEVENT04 = 0x324,
380    CSR_MHPMEVENT05 = 0x325,
381    CSR_MHPMEVENT06 = 0x326,
382    CSR_MHPMEVENT07 = 0x327,
383    CSR_MHPMEVENT08 = 0x328,
384    CSR_MHPMEVENT09 = 0x329,
385    CSR_MHPMEVENT10 = 0x32A,
386    CSR_MHPMEVENT11 = 0x32B,
387    CSR_MHPMEVENT12 = 0x32C,
388    CSR_MHPMEVENT13 = 0x32D,
389    CSR_MHPMEVENT14 = 0x32E,
390    CSR_MHPMEVENT15 = 0x32F,
391    CSR_MHPMEVENT16 = 0x330,
392    CSR_MHPMEVENT17 = 0x331,
393    CSR_MHPMEVENT18 = 0x332,
394    CSR_MHPMEVENT19 = 0x333,
395    CSR_MHPMEVENT20 = 0x334,
396    CSR_MHPMEVENT21 = 0x335,
397    CSR_MHPMEVENT22 = 0x336,
398    CSR_MHPMEVENT23 = 0x337,
399    CSR_MHPMEVENT24 = 0x338,
400    CSR_MHPMEVENT25 = 0x339,
401    CSR_MHPMEVENT26 = 0x33A,
402    CSR_MHPMEVENT27 = 0x33B,
403    CSR_MHPMEVENT28 = 0x33C,
404    CSR_MHPMEVENT29 = 0x33D,
405    CSR_MHPMEVENT30 = 0x33E,
406    CSR_MHPMEVENT31 = 0x33F,
407
408    CSR_TSELECT = 0x7A0,
409    CSR_TDATA1 = 0x7A1,
410    CSR_TDATA2 = 0x7A2,
411    CSR_TDATA3 = 0x7A3,
412    CSR_DCSR = 0x7B0,
413    CSR_DPC = 0x7B1,
414    CSR_DSCRATCH = 0x7B2
415};
416
417struct CSRMetadata
418{
419    const std::string name;
420    const int physIndex;
421};
422
423const std::map<int, CSRMetadata> CSRData = {
424    {CSR_USTATUS, {"ustatus", MISCREG_STATUS}},
425    {CSR_UIE, {"uie", MISCREG_IE}},
426    {CSR_UTVEC, {"utvec", MISCREG_UTVEC}},
427    {CSR_USCRATCH, {"uscratch", MISCREG_USCRATCH}},
428    {CSR_UEPC, {"uepc", MISCREG_UEPC}},
429    {CSR_UCAUSE, {"ucause", MISCREG_UCAUSE}},
430    {CSR_UTVAL, {"utval", MISCREG_UTVAL}},
431    {CSR_UIP, {"uip", MISCREG_IP}},
432    {CSR_FFLAGS, {"fflags", MISCREG_FFLAGS}},
433    {CSR_FRM, {"frm", MISCREG_FRM}},
434    {CSR_FCSR, {"fcsr", MISCREG_FFLAGS}}, // Actually FRM << 5 | FFLAGS
435    {CSR_CYCLE, {"cycle", MISCREG_CYCLE}},
436    {CSR_TIME, {"time", MISCREG_TIME}},
437    {CSR_INSTRET, {"instret", MISCREG_INSTRET}},
438    {CSR_HPMCOUNTER03, {"hpmcounter03", MISCREG_HPMCOUNTER03}},
439    {CSR_HPMCOUNTER04, {"hpmcounter04", MISCREG_HPMCOUNTER04}},
440    {CSR_HPMCOUNTER05, {"hpmcounter05", MISCREG_HPMCOUNTER05}},
441    {CSR_HPMCOUNTER06, {"hpmcounter06", MISCREG_HPMCOUNTER06}},
442    {CSR_HPMCOUNTER07, {"hpmcounter07", MISCREG_HPMCOUNTER07}},
443    {CSR_HPMCOUNTER08, {"hpmcounter08", MISCREG_HPMCOUNTER08}},
444    {CSR_HPMCOUNTER09, {"hpmcounter09", MISCREG_HPMCOUNTER09}},
445    {CSR_HPMCOUNTER10, {"hpmcounter10", MISCREG_HPMCOUNTER10}},
446    {CSR_HPMCOUNTER11, {"hpmcounter11", MISCREG_HPMCOUNTER11}},
447    {CSR_HPMCOUNTER12, {"hpmcounter12", MISCREG_HPMCOUNTER12}},
448    {CSR_HPMCOUNTER13, {"hpmcounter13", MISCREG_HPMCOUNTER13}},
449    {CSR_HPMCOUNTER14, {"hpmcounter14", MISCREG_HPMCOUNTER14}},
450    {CSR_HPMCOUNTER15, {"hpmcounter15", MISCREG_HPMCOUNTER15}},
451    {CSR_HPMCOUNTER16, {"hpmcounter16", MISCREG_HPMCOUNTER16}},
452    {CSR_HPMCOUNTER17, {"hpmcounter17", MISCREG_HPMCOUNTER17}},
453    {CSR_HPMCOUNTER18, {"hpmcounter18", MISCREG_HPMCOUNTER18}},
454    {CSR_HPMCOUNTER19, {"hpmcounter19", MISCREG_HPMCOUNTER19}},
455    {CSR_HPMCOUNTER20, {"hpmcounter20", MISCREG_HPMCOUNTER20}},
456    {CSR_HPMCOUNTER21, {"hpmcounter21", MISCREG_HPMCOUNTER21}},
457    {CSR_HPMCOUNTER22, {"hpmcounter22", MISCREG_HPMCOUNTER22}},
458    {CSR_HPMCOUNTER23, {"hpmcounter23", MISCREG_HPMCOUNTER23}},
459    {CSR_HPMCOUNTER24, {"hpmcounter24", MISCREG_HPMCOUNTER24}},
460    {CSR_HPMCOUNTER25, {"hpmcounter25", MISCREG_HPMCOUNTER25}},
461    {CSR_HPMCOUNTER26, {"hpmcounter26", MISCREG_HPMCOUNTER26}},
462    {CSR_HPMCOUNTER27, {"hpmcounter27", MISCREG_HPMCOUNTER27}},
463    {CSR_HPMCOUNTER28, {"hpmcounter28", MISCREG_HPMCOUNTER28}},
464    {CSR_HPMCOUNTER29, {"hpmcounter29", MISCREG_HPMCOUNTER29}},
465    {CSR_HPMCOUNTER30, {"hpmcounter30", MISCREG_HPMCOUNTER30}},
466    {CSR_HPMCOUNTER31, {"hpmcounter31", MISCREG_HPMCOUNTER31}},
467
468    {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}},
469    {CSR_SEDELEG, {"sedeleg", MISCREG_SEDELEG}},
470    {CSR_SIDELEG, {"sideleg", MISCREG_SIDELEG}},
471    {CSR_SIE, {"sie", MISCREG_IE}},
472    {CSR_STVEC, {"stvec", MISCREG_STVEC}},
473    {CSR_SSCRATCH, {"sscratch", MISCREG_SSCRATCH}},
474    {CSR_SEPC, {"sepc", MISCREG_SEPC}},
475    {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}},
476    {CSR_STVAL, {"stval", MISCREG_STVAL}},
477    {CSR_SIP, {"sip", MISCREG_IP}},
478    {CSR_SATP, {"satp", MISCREG_SATP}},
479
480    {CSR_MVENDORID, {"mvendorid", MISCREG_VENDORID}},
481    {CSR_MARCHID, {"marchid", MISCREG_ARCHID}},
482    {CSR_MIMPID, {"mimpid", MISCREG_IMPID}},
483    {CSR_MHARTID, {"mhartid", MISCREG_HARTID}},
484    {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},
485    {CSR_MISA, {"misa", MISCREG_ISA}},
486    {CSR_MEDELEG, {"medeleg", MISCREG_MEDELEG}},
487    {CSR_MIDELEG, {"mideleg", MISCREG_MIDELEG}},
488    {CSR_MIE, {"mie", MISCREG_IE}},
489    {CSR_MTVEC, {"mtvec", MISCREG_MTVEC}},
490    {CSR_MSCRATCH, {"mscratch", MISCREG_MSCRATCH}},
491    {CSR_MEPC, {"mepc", MISCREG_MEPC}},
492    {CSR_MCAUSE, {"mcause", MISCREG_MCAUSE}},
493    {CSR_MTVAL, {"mtval", MISCREG_MTVAL}},
494    {CSR_MIP, {"mip", MISCREG_IP}},
495    {CSR_PMPCFG0, {"pmpcfg0", MISCREG_PMPCFG0}},
496    // pmpcfg1 rv32 only
497    {CSR_PMPCFG2, {"pmpcfg2", MISCREG_PMPCFG2}},
498    // pmpcfg3 rv32 only
499    {CSR_PMPADDR00, {"pmpaddr0", MISCREG_PMPADDR00}},
500    {CSR_PMPADDR01, {"pmpaddr1", MISCREG_PMPADDR01}},
501    {CSR_PMPADDR02, {"pmpaddr2", MISCREG_PMPADDR02}},
502    {CSR_PMPADDR03, {"pmpaddr3", MISCREG_PMPADDR03}},
503    {CSR_PMPADDR04, {"pmpaddr4", MISCREG_PMPADDR04}},
504    {CSR_PMPADDR05, {"pmpaddr5", MISCREG_PMPADDR05}},
505    {CSR_PMPADDR06, {"pmpaddr6", MISCREG_PMPADDR06}},
506    {CSR_PMPADDR07, {"pmpaddr7", MISCREG_PMPADDR07}},
507    {CSR_PMPADDR08, {"pmpaddr8", MISCREG_PMPADDR08}},
508    {CSR_PMPADDR09, {"pmpaddr9", MISCREG_PMPADDR09}},
509    {CSR_PMPADDR10, {"pmpaddr10", MISCREG_PMPADDR10}},
510    {CSR_PMPADDR11, {"pmpaddr11", MISCREG_PMPADDR11}},
511    {CSR_PMPADDR12, {"pmpaddr12", MISCREG_PMPADDR12}},
512    {CSR_PMPADDR13, {"pmpaddr13", MISCREG_PMPADDR13}},
513    {CSR_PMPADDR14, {"pmpaddr14", MISCREG_PMPADDR14}},
514    {CSR_PMPADDR15, {"pmpaddr15", MISCREG_PMPADDR15}},
515    {CSR_MCYCLE, {"mcycle", MISCREG_CYCLE}},
516    {CSR_MINSTRET, {"minstret", MISCREG_INSTRET}},
517    {CSR_MHPMCOUNTER03, {"mhpmcounter03", MISCREG_HPMCOUNTER03}},
518    {CSR_MHPMCOUNTER04, {"mhpmcounter04", MISCREG_HPMCOUNTER04}},
519    {CSR_MHPMCOUNTER05, {"mhpmcounter05", MISCREG_HPMCOUNTER05}},
520    {CSR_MHPMCOUNTER06, {"mhpmcounter06", MISCREG_HPMCOUNTER06}},
521    {CSR_MHPMCOUNTER07, {"mhpmcounter07", MISCREG_HPMCOUNTER07}},
522    {CSR_MHPMCOUNTER08, {"mhpmcounter08", MISCREG_HPMCOUNTER08}},
523    {CSR_MHPMCOUNTER09, {"mhpmcounter09", MISCREG_HPMCOUNTER09}},
524    {CSR_MHPMCOUNTER10, {"mhpmcounter10", MISCREG_HPMCOUNTER10}},
525    {CSR_MHPMCOUNTER11, {"mhpmcounter11", MISCREG_HPMCOUNTER11}},
526    {CSR_MHPMCOUNTER12, {"mhpmcounter12", MISCREG_HPMCOUNTER12}},
527    {CSR_MHPMCOUNTER13, {"mhpmcounter13", MISCREG_HPMCOUNTER13}},
528    {CSR_MHPMCOUNTER14, {"mhpmcounter14", MISCREG_HPMCOUNTER14}},
529    {CSR_MHPMCOUNTER15, {"mhpmcounter15", MISCREG_HPMCOUNTER15}},
530    {CSR_MHPMCOUNTER16, {"mhpmcounter16", MISCREG_HPMCOUNTER16}},
531    {CSR_MHPMCOUNTER17, {"mhpmcounter17", MISCREG_HPMCOUNTER17}},
532    {CSR_MHPMCOUNTER18, {"mhpmcounter18", MISCREG_HPMCOUNTER18}},
533    {CSR_MHPMCOUNTER19, {"mhpmcounter19", MISCREG_HPMCOUNTER19}},
534    {CSR_MHPMCOUNTER20, {"mhpmcounter20", MISCREG_HPMCOUNTER20}},
535    {CSR_MHPMCOUNTER21, {"mhpmcounter21", MISCREG_HPMCOUNTER21}},
536    {CSR_MHPMCOUNTER22, {"mhpmcounter22", MISCREG_HPMCOUNTER22}},
537    {CSR_MHPMCOUNTER23, {"mhpmcounter23", MISCREG_HPMCOUNTER23}},
538    {CSR_MHPMCOUNTER24, {"mhpmcounter24", MISCREG_HPMCOUNTER24}},
539    {CSR_MHPMCOUNTER25, {"mhpmcounter25", MISCREG_HPMCOUNTER25}},
540    {CSR_MHPMCOUNTER26, {"mhpmcounter26", MISCREG_HPMCOUNTER26}},
541    {CSR_MHPMCOUNTER27, {"mhpmcounter27", MISCREG_HPMCOUNTER27}},
542    {CSR_MHPMCOUNTER28, {"mhpmcounter28", MISCREG_HPMCOUNTER28}},
543    {CSR_MHPMCOUNTER29, {"mhpmcounter29", MISCREG_HPMCOUNTER29}},
544    {CSR_MHPMCOUNTER30, {"mhpmcounter30", MISCREG_HPMCOUNTER30}},
545    {CSR_MHPMCOUNTER31, {"mhpmcounter31", MISCREG_HPMCOUNTER31}},
546    {CSR_MHPMEVENT03, {"mhpmevent03", MISCREG_HPMEVENT03}},
547    {CSR_MHPMEVENT04, {"mhpmevent04", MISCREG_HPMEVENT04}},
548    {CSR_MHPMEVENT05, {"mhpmevent05", MISCREG_HPMEVENT05}},
549    {CSR_MHPMEVENT06, {"mhpmevent06", MISCREG_HPMEVENT06}},
550    {CSR_MHPMEVENT07, {"mhpmevent07", MISCREG_HPMEVENT07}},
551    {CSR_MHPMEVENT08, {"mhpmevent08", MISCREG_HPMEVENT08}},
552    {CSR_MHPMEVENT09, {"mhpmevent09", MISCREG_HPMEVENT09}},
553    {CSR_MHPMEVENT10, {"mhpmevent10", MISCREG_HPMEVENT10}},
554    {CSR_MHPMEVENT11, {"mhpmevent11", MISCREG_HPMEVENT11}},
555    {CSR_MHPMEVENT12, {"mhpmevent12", MISCREG_HPMEVENT12}},
556    {CSR_MHPMEVENT13, {"mhpmevent13", MISCREG_HPMEVENT13}},
557    {CSR_MHPMEVENT14, {"mhpmevent14", MISCREG_HPMEVENT14}},
558    {CSR_MHPMEVENT15, {"mhpmevent15", MISCREG_HPMEVENT15}},
559    {CSR_MHPMEVENT16, {"mhpmevent16", MISCREG_HPMEVENT16}},
560    {CSR_MHPMEVENT17, {"mhpmevent17", MISCREG_HPMEVENT17}},
561    {CSR_MHPMEVENT18, {"mhpmevent18", MISCREG_HPMEVENT18}},
562    {CSR_MHPMEVENT19, {"mhpmevent19", MISCREG_HPMEVENT19}},
563    {CSR_MHPMEVENT20, {"mhpmevent20", MISCREG_HPMEVENT20}},
564    {CSR_MHPMEVENT21, {"mhpmevent21", MISCREG_HPMEVENT21}},
565    {CSR_MHPMEVENT22, {"mhpmevent22", MISCREG_HPMEVENT22}},
566    {CSR_MHPMEVENT23, {"mhpmevent23", MISCREG_HPMEVENT23}},
567    {CSR_MHPMEVENT24, {"mhpmevent24", MISCREG_HPMEVENT24}},
568    {CSR_MHPMEVENT25, {"mhpmevent25", MISCREG_HPMEVENT25}},
569    {CSR_MHPMEVENT26, {"mhpmevent26", MISCREG_HPMEVENT26}},
570    {CSR_MHPMEVENT27, {"mhpmevent27", MISCREG_HPMEVENT27}},
571    {CSR_MHPMEVENT28, {"mhpmevent28", MISCREG_HPMEVENT28}},
572    {CSR_MHPMEVENT29, {"mhpmevent29", MISCREG_HPMEVENT29}},
573    {CSR_MHPMEVENT30, {"mhpmevent30", MISCREG_HPMEVENT30}},
574    {CSR_MHPMEVENT31, {"mhpmevent31", MISCREG_HPMEVENT31}},
575
576    {CSR_TSELECT, {"tselect", MISCREG_TSELECT}},
577    {CSR_TDATA1, {"tdata1", MISCREG_TDATA1}},
578    {CSR_TDATA2, {"tdata2", MISCREG_TDATA2}},
579    {CSR_TDATA3, {"tdata3", MISCREG_TDATA3}},
580    {CSR_DCSR, {"dcsr", MISCREG_DCSR}},
581    {CSR_DPC, {"dpc", MISCREG_DPC}},
582    {CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}}
583};
584
585/**
586 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
587 * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that
588 * uses these fields is the MSTATUS register, which is shadowed by two others
589 * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see
590 * the fields for higher privileges.
591 */
592BitUnion64(STATUS)
593    Bitfield<63> sd;
594    Bitfield<35, 34> sxl;
595    Bitfield<33, 32> uxl;
596    Bitfield<22> tsr;
597    Bitfield<21> tw;
598    Bitfield<20> tvm;
599    Bitfield<19> mxr;
600    Bitfield<18> sum;
601    Bitfield<17> mprv;
602    Bitfield<16, 15> xs;
603    Bitfield<14, 13> fs;
604    Bitfield<12, 11> mpp;
605    Bitfield<8> spp;
606    Bitfield<7> mpie;
607    Bitfield<5> spie;
608    Bitfield<4> upie;
609    Bitfield<3> mie;
610    Bitfield<1> sie;
611    Bitfield<0> uie;
612EndBitUnion(STATUS)
613
614/**
615 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
616 * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP
617 * and MIE registers have the same fields, so accesses to either should use
618 * this bit union.
619 */
620BitUnion64(INTERRUPT)
621    Bitfield<11> mei;
622    Bitfield<9> sei;
623    Bitfield<8> uei;
624    Bitfield<7> mti;
625    Bitfield<5> sti;
626    Bitfield<4> uti;
627    Bitfield<3> msi;
628    Bitfield<1> ssi;
629    Bitfield<0> usi;
630EndBitUnion(INTERRUPT)
631
632const off_t MXL_OFFSET = (sizeof(MiscReg) * 8 - 2);
633const off_t SXL_OFFSET = 34;
634const off_t UXL_OFFSET = 32;
635const off_t FS_OFFSET = 13;
636const off_t FRM_OFFSET = 5;
637
638const MiscReg ISA_MXL_MASK = 3ULL << MXL_OFFSET;
639const MiscReg ISA_EXT_MASK = mask(26);
640const MiscReg MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
641
642const MiscReg STATUS_SD_MASK = 1ULL << ((sizeof(MiscReg) * 8) - 1);
643const MiscReg STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
644const MiscReg STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
645const MiscReg STATUS_TSR_MASK = 1ULL << 22;
646const MiscReg STATUS_TW_MASK = 1ULL << 21;
647const MiscReg STATUS_TVM_MASK = 1ULL << 20;
648const MiscReg STATUS_MXR_MASK = 1ULL << 19;
649const MiscReg STATUS_SUM_MASK = 1ULL << 18;
650const MiscReg STATUS_MPRV_MASK = 1ULL << 17;
651const MiscReg STATUS_XS_MASK = 3ULL << 15;
652const MiscReg STATUS_FS_MASK = 3ULL << FS_OFFSET;
653const MiscReg STATUS_MPP_MASK = 3ULL << 11;
654const MiscReg STATUS_SPP_MASK = 1ULL << 8;
655const MiscReg STATUS_MPIE_MASK = 1ULL << 7;
656const MiscReg STATUS_SPIE_MASK = 1ULL << 5;
657const MiscReg STATUS_UPIE_MASK = 1ULL << 4;
658const MiscReg STATUS_MIE_MASK = 1ULL << 3;
659const MiscReg STATUS_SIE_MASK = 1ULL << 1;
660const MiscReg STATUS_UIE_MASK = 1ULL << 0;
661const MiscReg MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
662                             STATUS_UXL_MASK | STATUS_TSR_MASK |
663                             STATUS_TW_MASK | STATUS_TVM_MASK |
664                             STATUS_MXR_MASK | STATUS_SUM_MASK |
665                             STATUS_MPRV_MASK | STATUS_XS_MASK |
666                             STATUS_FS_MASK | STATUS_MPP_MASK |
667                             STATUS_SPP_MASK | STATUS_MPIE_MASK |
668                             STATUS_SPIE_MASK | STATUS_UPIE_MASK |
669                             STATUS_MIE_MASK | STATUS_SIE_MASK |
670                             STATUS_UIE_MASK;
671const MiscReg SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
672                             STATUS_MXR_MASK | STATUS_SUM_MASK |
673                             STATUS_XS_MASK | STATUS_FS_MASK |
674                             STATUS_SPP_MASK | STATUS_SPIE_MASK |
675                             STATUS_UPIE_MASK | STATUS_SIE_MASK |
676                             STATUS_UIE_MASK;
677const MiscReg USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
678                             STATUS_SUM_MASK | STATUS_XS_MASK |
679                             STATUS_FS_MASK | STATUS_UPIE_MASK |
680                             STATUS_UIE_MASK;
681
682const MiscReg MEI_MASK = 1ULL << 11;
683const MiscReg SEI_MASK = 1ULL << 9;
684const MiscReg UEI_MASK = 1ULL << 8;
685const MiscReg MTI_MASK = 1ULL << 7;
686const MiscReg STI_MASK = 1ULL << 5;
687const MiscReg UTI_MASK = 1ULL << 4;
688const MiscReg MSI_MASK = 1ULL << 3;
689const MiscReg SSI_MASK = 1ULL << 1;
690const MiscReg USI_MASK = 1ULL << 0;
691const MiscReg MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
692                        MTI_MASK | STI_MASK | UTI_MASK |
693                        MSI_MASK | SSI_MASK | USI_MASK;
694const MiscReg SI_MASK = SEI_MASK | UEI_MASK |
695                        STI_MASK | UTI_MASK |
696                        SSI_MASK | USI_MASK;
697const MiscReg UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
698const MiscReg FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
699const MiscReg FRM_MASK = 0x7;
700
701const std::map<int, MiscReg> CSRMasks = {
702    {CSR_USTATUS, USTATUS_MASK},
703    {CSR_UIE, UI_MASK},
704    {CSR_UIP, UI_MASK},
705    {CSR_FFLAGS, FFLAGS_MASK},
706    {CSR_FRM, FRM_MASK},
707    {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
708    {CSR_SSTATUS, SSTATUS_MASK},
709    {CSR_SIE, SI_MASK},
710    {CSR_SIP, SI_MASK},
711    {CSR_MSTATUS, MSTATUS_MASK},
712    {CSR_MISA, MISA_MASK},
713    {CSR_MIE, MI_MASK},
714    {CSR_MIP, MI_MASK}
715};
716
717}
718
719#endif // __ARCH_RISCV_REGISTERS_HH__
720