operands.isa revision 11725:eb58f1bbeac8
16184SN/A// -*- mode:c++ -*- 26184SN/A 36184SN/A// Copyright (c) 2015 RISC-V Foundation 46184SN/A// Copyright (c) 2016 The University of Virginia 56184SN/A// All rights reserved. 66184SN/A// 76184SN/A// Redistribution and use in source and binary forms, with or without 86184SN/A// modification, are permitted provided that the following conditions are 96184SN/A// met: redistributions of source code must retain the above copyright 106184SN/A// notice, this list of conditions and the following disclaimer; 116184SN/A// redistributions in binary form must reproduce the above copyright 126184SN/A// notice, this list of conditions and the following disclaimer in the 136184SN/A// documentation and/or other materials provided with the distribution; 146184SN/A// neither the name of the copyright holders nor the names of its 156184SN/A// contributors may be used to endorse or promote products derived from 166184SN/A// this software without specific prior written permission. 176184SN/A// 186184SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 196184SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 206184SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 216184SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 226184SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 236184SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 246184SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 256184SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 266184SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 276184SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 286184SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 296184SN/A// 306184SN/A// Authors: Maxwell Walter 316184SN/A// Alec Roelke 326184SN/A 336184SN/Adef operand_types {{ 346226Snate@binkert.org 'sb' : 'int8_t', 358232Snate@binkert.org 'ub' : 'uint8_t', 366184SN/A 'sh' : 'int16_t', 3710785Sgope@wisc.edu 'uh' : 'uint16_t', 389480Snilay@cs.wisc.edu 'sw' : 'int32_t', 399480Snilay@cs.wisc.edu 'uw' : 'uint32_t', 4010785Sgope@wisc.edu 'sd' : 'int64_t', 416184SN/A 'ud' : 'uint64_t', 426184SN/A 'sf' : 'float', 436184SN/A 'df' : 'double' 446184SN/A}}; 456184SN/A 466184SN/Adef operands {{ 476184SN/A#General Purpose Integer Reg Operands 486184SN/A 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1), 496184SN/A 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2), 506184SN/A 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3), 516184SN/A 526184SN/A 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1), 536184SN/A 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1), 546184SN/A 'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2), 559480Snilay@cs.wisc.edu 'Fs1_bits': ('FloatReg', 'ud', 'FS1', 'IsFloating', 2), 566184SN/A 'Fs2': ('FloatReg', 'df', 'FS2', 'IsFloating', 3), 576184SN/A 'Fs2_bits': ('FloatReg', 'ud', 'FS2', 'IsFloating', 3), 586184SN/A 'Fs3': ('FloatReg', 'df', 'FS3', 'IsFloating', 4), 596184SN/A 'Fs3_bits': ('FloatReg', 'ud', 'FS3', 'IsFloating', 4), 606227Snate@binkert.org 619480Snilay@cs.wisc.edu#Memory Operand 626184SN/A 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5), 639480Snilay@cs.wisc.edu 646184SN/A#Program Counter Operands 656184SN/A 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7), 669480Snilay@cs.wisc.edu 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8), 676184SN/A}}; 689480Snilay@cs.wisc.edu