xref: /gem5/src/arch/riscv/isa/operands.isa

// -*- mode:c++ -*-

// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2016 The University of Virginia
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//
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// Authors: Maxwell Walter
//          Alec Roelke

def operand_types {{
    'sb' : 'int8_t',
    'ub' : 'uint8_t',
    'sh' : 'int16_t',
    'uh' : 'uint16_t',
    'sw' : 'int32_t',
    'uw' : 'uint32_t',
    'sd' : 'int64_t',
    'ud' : 'uint64_t',
}};

def operands {{
#General Purpose Integer Reg Operands
    'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
    'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
    'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),

#Memory Operand
    'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),

#Program Counter Operands
    'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
    'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
}};