includes.isa revision 12369 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are
9// met: redistributions of source code must retain the above copyright
10// notice, this list of conditions and the following disclaimer;
11// redistributions in binary form must reproduce the above copyright
12// notice, this list of conditions and the following disclaimer in the
13// documentation and/or other materials provided with the distribution;
14// neither the name of the copyright holders nor the names of its
15// contributors may be used to endorse or promote products derived from
16// this software without specific prior written permission.
17//
18// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Maxwell Walter
31//          Alec Roelke
32
33////////////////////////////////////////////////////////////////////
34//
35// Output include file directives.
36//
37
38output header {{
39#include <iomanip>
40#include <sstream>
41#include <string>
42#include <tuple>
43#include <vector>
44
45#include "arch/riscv/insts/amo.hh"
46#include "arch/riscv/insts/compressed.hh"
47#include "arch/riscv/insts/mem.hh"
48#include "arch/riscv/insts/standard.hh"
49#include "arch/riscv/insts/static_inst.hh"
50#include "arch/riscv/insts/unknown.hh"
51#include "cpu/static_inst.hh"
52#include "mem/packet.hh"
53#include "mem/request.hh"
54
55}};
56
57output decoder {{
58#include <cfenv>
59#include <cmath>
60#include <limits>
61#include <string>
62
63#include "arch/riscv/decoder.hh"
64#include "arch/riscv/faults.hh"
65#include "arch/riscv/tlb.hh"
66#include "base/cprintf.hh"
67#include "base/loader/symtab.hh"
68#include "cpu/thread_context.hh"
69#include "mem/packet.hh"
70#include "mem/request.hh"
71#include "sim/full_system.hh"
72
73using namespace RiscvISA;
74using namespace std;
75}};
76
77output exec {{
78#include <cfenv>
79#include <cmath>
80#include <string>
81#include <vector>
82
83#include "arch/generic/memhelpers.hh"
84#include "arch/riscv/faults.hh"
85#include "arch/riscv/registers.hh"
86#include "arch/riscv/utility.hh"
87#include "base/condcodes.hh"
88#include "cpu/base.hh"
89#include "cpu/exetrace.hh"
90#include "mem/packet.hh"
91#include "mem/packet_access.hh"
92#include "mem/request.hh"
93#include "sim/eventq.hh"
94#include "sim/full_system.hh"
95#include "sim/sim_events.hh"
96#include "sim/sim_exit.hh"
97#include "sim/system.hh"
98
99using namespace RiscvISA;
100using namespace std;
101}};
102