unknown.isa revision 12236:126ac9da6050 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are
9// met: redistributions of source code must retain the above copyright
10// notice, this list of conditions and the following disclaimer;
11// redistributions in binary form must reproduce the above copyright
12// notice, this list of conditions and the following disclaimer in the
13// documentation and/or other materials provided with the distribution;
14// neither the name of the copyright holders nor the names of its
15// contributors may be used to endorse or promote products derived from
16// this software without specific prior written permission.
17//
18// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Maxwell Walter
31//          Alec Roelke
32
33////////////////////////////////////////////////////////////////////
34//
35// Unknown instructions
36//
37
38output header {{
39    /**
40     * Static instruction class for unknown (illegal) instructions.
41     * These cause simulator termination if they are executed in a
42     * non-speculative mode.  This is a leaf class.
43     */
44    class Unknown : public RiscvStaticInst
45    {
46      public:
47        /// Constructor
48        Unknown(MachInst _machInst)
49            : RiscvStaticInst("unknown", _machInst, No_OpClass)
50        {
51            flags[IsNonSpeculative] = true;
52        }
53
54        Fault execute(ExecContext *, Trace::InstRecord *) const;
55
56        std::string
57        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
58    };
59}};
60
61output decoder {{
62    std::string
63    Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
64    {
65        return csprintf("unknown opcode 0x%02x", OPCODE);
66    }
67}};
68
69output exec {{
70    Fault
71    Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
72    {
73        Fault fault = std::make_shared<UnknownInstFault>();
74        return fault;
75    }
76}};
77
78def format Unknown() {{
79    decode_block = 'return new Unknown(machInst);\n'
80}};
81