standard.isa revision 12234
112119Sar4jc@virginia.edu// -*- mode:c++ -*- 212119Sar4jc@virginia.edu 312119Sar4jc@virginia.edu// Copyright (c) 2015 RISC-V Foundation 412119Sar4jc@virginia.edu// Copyright (c) 2016-2017 The University of Virginia 512119Sar4jc@virginia.edu// All rights reserved. 612119Sar4jc@virginia.edu// 712119Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 812119Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 912119Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 1012119Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 1112119Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 1212119Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 1312119Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 1412119Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 1512119Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 1612119Sar4jc@virginia.edu// this software without specific prior written permission. 1712119Sar4jc@virginia.edu// 1812119Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1912119Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2012119Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2112119Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2212119Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2312119Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2412119Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2512119Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2612119Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2712119Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2812119Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2912119Sar4jc@virginia.edu// 3012119Sar4jc@virginia.edu// Authors: Alec Roelke 3112119Sar4jc@virginia.edu 3212119Sar4jc@virginia.edu//////////////////////////////////////////////////////////////////// 3312119Sar4jc@virginia.edu// 3412119Sar4jc@virginia.edu// Integer instructions 3512119Sar4jc@virginia.edu// 3612119Sar4jc@virginia.eduoutput header {{ 3712119Sar4jc@virginia.edu /** 3812119Sar4jc@virginia.edu * Base class for operations that work only on registers 3912119Sar4jc@virginia.edu */ 4012119Sar4jc@virginia.edu class RegOp : public RiscvStaticInst 4112119Sar4jc@virginia.edu { 4212119Sar4jc@virginia.edu protected: 4312119Sar4jc@virginia.edu /// Constructor 4412119Sar4jc@virginia.edu RegOp(const char *mnem, MachInst _machInst, OpClass __opClass) 4512119Sar4jc@virginia.edu : RiscvStaticInst(mnem, _machInst, __opClass) 4612119Sar4jc@virginia.edu {} 4712119Sar4jc@virginia.edu 4812119Sar4jc@virginia.edu std::string 4912119Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 5012119Sar4jc@virginia.edu }; 5112119Sar4jc@virginia.edu 5212119Sar4jc@virginia.edu /** 5312119Sar4jc@virginia.edu * Base class for operations with signed immediates 5412119Sar4jc@virginia.edu */ 5512119Sar4jc@virginia.edu class ImmOp : public RiscvStaticInst 5612119Sar4jc@virginia.edu { 5712119Sar4jc@virginia.edu protected: 5812119Sar4jc@virginia.edu int64_t imm; 5912119Sar4jc@virginia.edu 6012119Sar4jc@virginia.edu /// Constructor 6112119Sar4jc@virginia.edu ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) 6212119Sar4jc@virginia.edu : RiscvStaticInst(mnem, _machInst, __opClass), imm(0) 6312119Sar4jc@virginia.edu {} 6412119Sar4jc@virginia.edu 6512119Sar4jc@virginia.edu virtual std::string 6612119Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 6712119Sar4jc@virginia.edu }; 6812119Sar4jc@virginia.edu 6912119Sar4jc@virginia.edu /** 7012119Sar4jc@virginia.edu * Base class for operations with unsigned immediates 7112119Sar4jc@virginia.edu */ 7212119Sar4jc@virginia.edu class UImmOp : public RiscvStaticInst 7312119Sar4jc@virginia.edu { 7412119Sar4jc@virginia.edu protected: 7512119Sar4jc@virginia.edu uint64_t imm; 7612119Sar4jc@virginia.edu 7712119Sar4jc@virginia.edu /// Constructor 7812119Sar4jc@virginia.edu UImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) 7912119Sar4jc@virginia.edu : RiscvStaticInst(mnem, _machInst, __opClass), imm(0) 8012119Sar4jc@virginia.edu {} 8112119Sar4jc@virginia.edu 8212119Sar4jc@virginia.edu virtual std::string 8312119Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 8412119Sar4jc@virginia.edu }; 8512119Sar4jc@virginia.edu 8612119Sar4jc@virginia.edu /** 8712119Sar4jc@virginia.edu * Base class for operations with branching 8812119Sar4jc@virginia.edu */ 8912119Sar4jc@virginia.edu class BranchOp : public ImmOp 9012119Sar4jc@virginia.edu { 9112119Sar4jc@virginia.edu protected: 9212119Sar4jc@virginia.edu /// Constructor 9312119Sar4jc@virginia.edu BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass) 9412119Sar4jc@virginia.edu : ImmOp(mnem, _machInst, __opClass) 9512119Sar4jc@virginia.edu {} 9612119Sar4jc@virginia.edu 9712119Sar4jc@virginia.edu using StaticInst::branchTarget; 9812119Sar4jc@virginia.edu 9912119Sar4jc@virginia.edu virtual RiscvISA::PCState 10012119Sar4jc@virginia.edu branchTarget(ThreadContext *tc) const 10112119Sar4jc@virginia.edu { 10212119Sar4jc@virginia.edu return StaticInst::branchTarget(tc); 10312119Sar4jc@virginia.edu } 10412119Sar4jc@virginia.edu 10512119Sar4jc@virginia.edu virtual RiscvISA::PCState 10612119Sar4jc@virginia.edu branchTarget(const RiscvISA::PCState &branchPC) const 10712119Sar4jc@virginia.edu { 10812119Sar4jc@virginia.edu return StaticInst::branchTarget(branchPC); 10912119Sar4jc@virginia.edu } 11012119Sar4jc@virginia.edu 11112119Sar4jc@virginia.edu virtual std::string 11212119Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 11312119Sar4jc@virginia.edu }; 11412119Sar4jc@virginia.edu 11512119Sar4jc@virginia.edu /** 11612119Sar4jc@virginia.edu * Base class for system operations 11712119Sar4jc@virginia.edu */ 11812119Sar4jc@virginia.edu class SystemOp : public RiscvStaticInst 11912119Sar4jc@virginia.edu { 12012119Sar4jc@virginia.edu public: 12112119Sar4jc@virginia.edu /// Constructor 12212119Sar4jc@virginia.edu SystemOp(const char *mnem, MachInst _machInst, OpClass __opClass) 12312119Sar4jc@virginia.edu : RiscvStaticInst(mnem, _machInst, __opClass) 12412119Sar4jc@virginia.edu {} 12512119Sar4jc@virginia.edu 12612119Sar4jc@virginia.edu std::string 12712119Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 12812119Sar4jc@virginia.edu { 12912119Sar4jc@virginia.edu return mnemonic; 13012119Sar4jc@virginia.edu } 13112119Sar4jc@virginia.edu }; 13212119Sar4jc@virginia.edu 13312119Sar4jc@virginia.edu /** 13412119Sar4jc@virginia.edu * Base class for CSR operations 13512119Sar4jc@virginia.edu */ 13612119Sar4jc@virginia.edu class CSROp : public RiscvStaticInst 13712119Sar4jc@virginia.edu { 13812119Sar4jc@virginia.edu protected: 13912119Sar4jc@virginia.edu uint64_t csr; 14012119Sar4jc@virginia.edu uint64_t uimm; 14112119Sar4jc@virginia.edu 14212119Sar4jc@virginia.edu public: 14312119Sar4jc@virginia.edu /// Constructor 14412119Sar4jc@virginia.edu CSROp(const char *mnem, MachInst _machInst, OpClass __opClass) 14512119Sar4jc@virginia.edu : RiscvStaticInst(mnem, _machInst, __opClass), 14612119Sar4jc@virginia.edu csr(FUNCT12), uimm(CSRIMM) 14712119Sar4jc@virginia.edu {} 14812119Sar4jc@virginia.edu 14912119Sar4jc@virginia.edu std::string 15012119Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 15112119Sar4jc@virginia.edu }; 15212119Sar4jc@virginia.edu}}; 15312119Sar4jc@virginia.edu 15412119Sar4jc@virginia.edu//Outputs to decoder.cc 15512119Sar4jc@virginia.eduoutput decoder {{ 15612119Sar4jc@virginia.edu std::string 15712119Sar4jc@virginia.edu RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 15812119Sar4jc@virginia.edu { 15912119Sar4jc@virginia.edu std::stringstream ss; 16012119Sar4jc@virginia.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << 16112119Sar4jc@virginia.edu registerName(_srcRegIdx[0]) << ", " << 16212119Sar4jc@virginia.edu registerName(_srcRegIdx[1]); 16312119Sar4jc@virginia.edu return ss.str(); 16412119Sar4jc@virginia.edu } 16512119Sar4jc@virginia.edu 16612119Sar4jc@virginia.edu std::string 16712119Sar4jc@virginia.edu CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 16812119Sar4jc@virginia.edu { 16912119Sar4jc@virginia.edu std::stringstream ss; 17012119Sar4jc@virginia.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "; 17112119Sar4jc@virginia.edu if (_numSrcRegs > 0) 17212119Sar4jc@virginia.edu ss << registerName(_srcRegIdx[0]) << ", "; 17312119Sar4jc@virginia.edu ss << MiscRegNames.at(csr); 17412119Sar4jc@virginia.edu return ss.str(); 17512119Sar4jc@virginia.edu } 17612119Sar4jc@virginia.edu}}; 17712119Sar4jc@virginia.edu 17812119Sar4jc@virginia.edudef template ImmDeclare {{ 17912119Sar4jc@virginia.edu // 18012119Sar4jc@virginia.edu // Static instruction class for "%(mnemonic)s". 18112119Sar4jc@virginia.edu // 18212119Sar4jc@virginia.edu class %(class_name)s : public %(base_class)s 18312119Sar4jc@virginia.edu { 18412119Sar4jc@virginia.edu public: 18512119Sar4jc@virginia.edu /// Constructor. 18612119Sar4jc@virginia.edu %(class_name)s(MachInst machInst); 18712119Sar4jc@virginia.edu %(BasicExecDeclare)s 18812119Sar4jc@virginia.edu std::string generateDisassembly(Addr pc, 18912119Sar4jc@virginia.edu const SymbolTable *symtab) const override; 19012119Sar4jc@virginia.edu }; 19112119Sar4jc@virginia.edu}}; 19212119Sar4jc@virginia.edu 19312119Sar4jc@virginia.edudef template ImmConstructor {{ 19412119Sar4jc@virginia.edu %(class_name)s::%(class_name)s(MachInst machInst) 19512119Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 19612119Sar4jc@virginia.edu { 19712119Sar4jc@virginia.edu %(constructor)s; 19812119Sar4jc@virginia.edu %(imm_code)s; 19912119Sar4jc@virginia.edu } 20012119Sar4jc@virginia.edu}}; 20112119Sar4jc@virginia.edu 20212119Sar4jc@virginia.edudef template ImmExecute {{ 20312119Sar4jc@virginia.edu Fault 20412234Sgabeblack@google.com %(class_name)s::execute( 20512234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 20612119Sar4jc@virginia.edu { 20712119Sar4jc@virginia.edu Fault fault = NoFault; 20812119Sar4jc@virginia.edu 20912119Sar4jc@virginia.edu %(op_decl)s; 21012119Sar4jc@virginia.edu %(op_rd)s; 21112119Sar4jc@virginia.edu if (fault == NoFault) { 21212119Sar4jc@virginia.edu %(code)s; 21312119Sar4jc@virginia.edu if (fault == NoFault) { 21412119Sar4jc@virginia.edu %(op_wb)s; 21512119Sar4jc@virginia.edu } 21612119Sar4jc@virginia.edu } 21712119Sar4jc@virginia.edu return fault; 21812119Sar4jc@virginia.edu } 21912119Sar4jc@virginia.edu 22012119Sar4jc@virginia.edu std::string 22112119Sar4jc@virginia.edu %(class_name)s::generateDisassembly(Addr pc, 22212119Sar4jc@virginia.edu const SymbolTable *symtab) const 22312119Sar4jc@virginia.edu { 22412119Sar4jc@virginia.edu std::vector<RegId> indices = {%(regs)s}; 22512119Sar4jc@virginia.edu std::stringstream ss; 22612119Sar4jc@virginia.edu ss << mnemonic << ' '; 22712119Sar4jc@virginia.edu for (const RegId& idx: indices) 22812119Sar4jc@virginia.edu ss << registerName(idx) << ", "; 22912119Sar4jc@virginia.edu ss << imm; 23012119Sar4jc@virginia.edu return ss.str(); 23112119Sar4jc@virginia.edu } 23212119Sar4jc@virginia.edu}}; 23312119Sar4jc@virginia.edu 23412119Sar4jc@virginia.edudef template BranchDeclare {{ 23512119Sar4jc@virginia.edu // 23612119Sar4jc@virginia.edu // Static instruction class for "%(mnemonic)s". 23712119Sar4jc@virginia.edu // 23812119Sar4jc@virginia.edu class %(class_name)s : public %(base_class)s 23912119Sar4jc@virginia.edu { 24012119Sar4jc@virginia.edu public: 24112119Sar4jc@virginia.edu /// Constructor. 24212119Sar4jc@virginia.edu %(class_name)s(MachInst machInst); 24312119Sar4jc@virginia.edu %(BasicExecDeclare)s 24412119Sar4jc@virginia.edu 24512119Sar4jc@virginia.edu std::string 24612119Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const override; 24712119Sar4jc@virginia.edu 24812119Sar4jc@virginia.edu RiscvISA::PCState 24912119Sar4jc@virginia.edu branchTarget(const RiscvISA::PCState &branchPC) const override; 25012119Sar4jc@virginia.edu 25112119Sar4jc@virginia.edu using StaticInst::branchTarget; 25212119Sar4jc@virginia.edu }; 25312119Sar4jc@virginia.edu}}; 25412119Sar4jc@virginia.edu 25512119Sar4jc@virginia.edudef template BranchExecute {{ 25612119Sar4jc@virginia.edu Fault 25712234Sgabeblack@google.com %(class_name)s::execute(ExecContext *xc, 25812119Sar4jc@virginia.edu Trace::InstRecord *traceData) const 25912119Sar4jc@virginia.edu { 26012119Sar4jc@virginia.edu Fault fault = NoFault; 26112119Sar4jc@virginia.edu 26212119Sar4jc@virginia.edu %(op_decl)s; 26312119Sar4jc@virginia.edu %(op_rd)s; 26412119Sar4jc@virginia.edu if (fault == NoFault) { 26512119Sar4jc@virginia.edu %(code)s; 26612119Sar4jc@virginia.edu if (fault == NoFault) { 26712119Sar4jc@virginia.edu %(op_wb)s; 26812119Sar4jc@virginia.edu } 26912119Sar4jc@virginia.edu } 27012119Sar4jc@virginia.edu return fault; 27112119Sar4jc@virginia.edu } 27212119Sar4jc@virginia.edu 27312119Sar4jc@virginia.edu RiscvISA::PCState 27412119Sar4jc@virginia.edu %(class_name)s::branchTarget(const RiscvISA::PCState &branchPC) const 27512119Sar4jc@virginia.edu { 27612119Sar4jc@virginia.edu return branchPC.pc() + imm; 27712119Sar4jc@virginia.edu } 27812119Sar4jc@virginia.edu 27912119Sar4jc@virginia.edu std::string 28012119Sar4jc@virginia.edu %(class_name)s::generateDisassembly(Addr pc, 28112119Sar4jc@virginia.edu const SymbolTable *symtab) const 28212119Sar4jc@virginia.edu { 28312119Sar4jc@virginia.edu std::vector<RegId> indices = {%(regs)s}; 28412119Sar4jc@virginia.edu std::stringstream ss; 28512119Sar4jc@virginia.edu ss << mnemonic << ' '; 28612119Sar4jc@virginia.edu for (const RegId& idx: indices) 28712119Sar4jc@virginia.edu ss << registerName(idx) << ", "; 28812119Sar4jc@virginia.edu ss << imm; 28912119Sar4jc@virginia.edu return ss.str(); 29012119Sar4jc@virginia.edu } 29112119Sar4jc@virginia.edu}}; 29212119Sar4jc@virginia.edu 29312119Sar4jc@virginia.edudef template JumpDeclare {{ 29412119Sar4jc@virginia.edu // 29512119Sar4jc@virginia.edu // Static instruction class for "%(mnemonic)s". 29612119Sar4jc@virginia.edu // 29712119Sar4jc@virginia.edu class %(class_name)s : public %(base_class)s 29812119Sar4jc@virginia.edu { 29912119Sar4jc@virginia.edu public: 30012119Sar4jc@virginia.edu /// Constructor. 30112119Sar4jc@virginia.edu %(class_name)s(MachInst machInst); 30212119Sar4jc@virginia.edu %(BasicExecDeclare)s 30312119Sar4jc@virginia.edu 30412119Sar4jc@virginia.edu std::string 30512119Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const override; 30612119Sar4jc@virginia.edu 30712119Sar4jc@virginia.edu RiscvISA::PCState 30812119Sar4jc@virginia.edu branchTarget(ThreadContext *tc) const override; 30912119Sar4jc@virginia.edu 31012119Sar4jc@virginia.edu using StaticInst::branchTarget; 31112119Sar4jc@virginia.edu }; 31212119Sar4jc@virginia.edu}}; 31312119Sar4jc@virginia.edu 31412119Sar4jc@virginia.edudef template JumpExecute {{ 31512119Sar4jc@virginia.edu Fault 31612234Sgabeblack@google.com %(class_name)s::execute( 31712234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 31812119Sar4jc@virginia.edu { 31912119Sar4jc@virginia.edu Fault fault = NoFault; 32012119Sar4jc@virginia.edu 32112119Sar4jc@virginia.edu %(op_decl)s; 32212119Sar4jc@virginia.edu %(op_rd)s; 32312119Sar4jc@virginia.edu if (fault == NoFault) { 32412119Sar4jc@virginia.edu %(code)s; 32512119Sar4jc@virginia.edu if (fault == NoFault) { 32612119Sar4jc@virginia.edu %(op_wb)s; 32712119Sar4jc@virginia.edu } 32812119Sar4jc@virginia.edu } 32912119Sar4jc@virginia.edu return fault; 33012119Sar4jc@virginia.edu } 33112119Sar4jc@virginia.edu 33212119Sar4jc@virginia.edu RiscvISA::PCState 33312119Sar4jc@virginia.edu %(class_name)s::branchTarget(ThreadContext *tc) const 33412119Sar4jc@virginia.edu { 33512119Sar4jc@virginia.edu PCState pc = tc->pcState(); 33612119Sar4jc@virginia.edu pc.set((tc->readIntReg(_srcRegIdx[0].index()) + imm)&~0x1); 33712119Sar4jc@virginia.edu return pc; 33812119Sar4jc@virginia.edu } 33912119Sar4jc@virginia.edu 34012119Sar4jc@virginia.edu std::string 34112119Sar4jc@virginia.edu %(class_name)s::generateDisassembly(Addr pc, 34212119Sar4jc@virginia.edu const SymbolTable *symtab) const 34312119Sar4jc@virginia.edu { 34412119Sar4jc@virginia.edu std::vector<RegId> indices = {%(regs)s}; 34512119Sar4jc@virginia.edu std::stringstream ss; 34612119Sar4jc@virginia.edu ss << mnemonic << ' '; 34712119Sar4jc@virginia.edu for (const RegId& idx: indices) 34812119Sar4jc@virginia.edu ss << registerName(idx) << ", "; 34912119Sar4jc@virginia.edu ss << imm; 35012119Sar4jc@virginia.edu return ss.str(); 35112119Sar4jc@virginia.edu } 35212119Sar4jc@virginia.edu}}; 35312119Sar4jc@virginia.edu 35412119Sar4jc@virginia.edudef format ROp(code, *opt_flags) {{ 35512119Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'RegOp', code, opt_flags) 35612119Sar4jc@virginia.edu header_output = BasicDeclare.subst(iop) 35712119Sar4jc@virginia.edu decoder_output = BasicConstructor.subst(iop) 35812119Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 35912119Sar4jc@virginia.edu exec_output = BasicExecute.subst(iop) 36012119Sar4jc@virginia.edu}}; 36112119Sar4jc@virginia.edu 36212119Sar4jc@virginia.edudef format IOp(code, *opt_flags) {{ 36312119Sar4jc@virginia.edu imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);' 36412119Sar4jc@virginia.edu regs = ['_destRegIdx[0]','_srcRegIdx[0]'] 36512119Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'ImmOp', 36612119Sar4jc@virginia.edu {'code': code, 'imm_code': imm_code, 36712119Sar4jc@virginia.edu 'regs': ','.join(regs)}, opt_flags) 36812119Sar4jc@virginia.edu header_output = ImmDeclare.subst(iop) 36912119Sar4jc@virginia.edu decoder_output = ImmConstructor.subst(iop) 37012119Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 37112119Sar4jc@virginia.edu exec_output = ImmExecute.subst(iop) 37212119Sar4jc@virginia.edu}}; 37312119Sar4jc@virginia.edu 37412119Sar4jc@virginia.edudef format BOp(code, *opt_flags) {{ 37512119Sar4jc@virginia.edu imm_code = """ 37612119Sar4jc@virginia.edu imm |= BIMM12BIT11 << 11; 37712119Sar4jc@virginia.edu imm |= BIMM12BITS4TO1 << 1; 37812119Sar4jc@virginia.edu imm |= BIMM12BITS10TO5 << 5; 37912119Sar4jc@virginia.edu if (IMMSIGN > 0) 38012119Sar4jc@virginia.edu imm |= ~((uint64_t)0xFFF); 38112119Sar4jc@virginia.edu """ 38212119Sar4jc@virginia.edu regs = ['_srcRegIdx[0]','_srcRegIdx[1]'] 38312119Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'BranchOp', 38412119Sar4jc@virginia.edu {'code': code, 'imm_code': imm_code, 38512119Sar4jc@virginia.edu 'regs': ','.join(regs)}, opt_flags) 38612119Sar4jc@virginia.edu header_output = BranchDeclare.subst(iop) 38712119Sar4jc@virginia.edu decoder_output = ImmConstructor.subst(iop) 38812119Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 38912119Sar4jc@virginia.edu exec_output = BranchExecute.subst(iop) 39012119Sar4jc@virginia.edu}}; 39112119Sar4jc@virginia.edu 39212119Sar4jc@virginia.edudef format Jump(code, *opt_flags) {{ 39312119Sar4jc@virginia.edu imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);' 39412119Sar4jc@virginia.edu regs = ['_destRegIdx[0]','_srcRegIdx[0]'] 39512119Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'BranchOp', 39612119Sar4jc@virginia.edu {'code': code, 'imm_code': imm_code, 39712119Sar4jc@virginia.edu 'regs': ','.join(regs)}, opt_flags) 39812119Sar4jc@virginia.edu header_output = JumpDeclare.subst(iop) 39912119Sar4jc@virginia.edu decoder_output = ImmConstructor.subst(iop) 40012119Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 40112119Sar4jc@virginia.edu exec_output = JumpExecute.subst(iop) 40212119Sar4jc@virginia.edu}}; 40312119Sar4jc@virginia.edu 40412119Sar4jc@virginia.edudef format UOp(code, *opt_flags) {{ 40512119Sar4jc@virginia.edu imm_code = 'imm = (int32_t)(IMM20 << 12);' 40612119Sar4jc@virginia.edu regs = ['_destRegIdx[0]'] 40712119Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'ImmOp', 40812119Sar4jc@virginia.edu {'code': code, 'imm_code': imm_code, 40912119Sar4jc@virginia.edu 'regs': ','.join(regs)}, opt_flags) 41012119Sar4jc@virginia.edu header_output = ImmDeclare.subst(iop) 41112119Sar4jc@virginia.edu decoder_output = ImmConstructor.subst(iop) 41212119Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 41312119Sar4jc@virginia.edu exec_output = ImmExecute.subst(iop) 41412119Sar4jc@virginia.edu}}; 41512119Sar4jc@virginia.edu 41612119Sar4jc@virginia.edudef format JOp(code, *opt_flags) {{ 41712119Sar4jc@virginia.edu imm_code = """ 41812119Sar4jc@virginia.edu imm |= UJIMMBITS19TO12 << 12; 41912119Sar4jc@virginia.edu imm |= UJIMMBIT11 << 11; 42012119Sar4jc@virginia.edu imm |= UJIMMBITS10TO1 << 1; 42112119Sar4jc@virginia.edu if (IMMSIGN > 0) 42212119Sar4jc@virginia.edu imm |= ~((uint64_t)0xFFFFF); 42312119Sar4jc@virginia.edu """ 42412119Sar4jc@virginia.edu pc = 'pc.set(pc.pc() + imm);' 42512119Sar4jc@virginia.edu regs = ['_destRegIdx[0]'] 42612119Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'BranchOp', 42712119Sar4jc@virginia.edu {'code': code, 'imm_code': imm_code, 42812119Sar4jc@virginia.edu 'regs': ','.join(regs)}, opt_flags) 42912119Sar4jc@virginia.edu header_output = BranchDeclare.subst(iop) 43012119Sar4jc@virginia.edu decoder_output = ImmConstructor.subst(iop) 43112119Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 43212119Sar4jc@virginia.edu exec_output = BranchExecute.subst(iop) 43312119Sar4jc@virginia.edu}}; 43412119Sar4jc@virginia.edu 43512119Sar4jc@virginia.edudef format SystemOp(code, *opt_flags) {{ 43612119Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'SystemOp', code, opt_flags) 43712119Sar4jc@virginia.edu header_output = BasicDeclare.subst(iop) 43812119Sar4jc@virginia.edu decoder_output = BasicConstructor.subst(iop) 43912119Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 44012119Sar4jc@virginia.edu exec_output = BasicExecute.subst(iop) 44112119Sar4jc@virginia.edu}}; 44212119Sar4jc@virginia.edu 44312119Sar4jc@virginia.edudef format CSROp(code, *opt_flags) {{ 44412119Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'CSROp', code, opt_flags) 44512119Sar4jc@virginia.edu header_output = BasicDeclare.subst(iop) 44612119Sar4jc@virginia.edu decoder_output = BasicConstructor.subst(iop) 44712119Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 44812119Sar4jc@virginia.edu exec_output = BasicExecute.subst(iop) 44912234Sgabeblack@google.com}}; 450