compressed.isa revision 12369:6811cd264242 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are
9// met: redistributions of source code must retain the above copyright
10// notice, this list of conditions and the following disclaimer;
11// redistributions in binary form must reproduce the above copyright
12// notice, this list of conditions and the following disclaimer in the
13// documentation and/or other materials provided with the distribution;
14// neither the name of the copyright holders nor the names of its
15// contributors may be used to endorse or promote products derived from
16// this software without specific prior written permission.
17//
18// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Alec Roelke
31def format CROp(code, *opt_flags) {{
32    iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
33    header_output = BasicDeclare.subst(iop)
34    decoder_output = BasicConstructor.subst(iop)
35    decode_block = BasicDecode.subst(iop)
36    exec_output = BasicExecute.subst(iop)
37}};
38
39def format CIOp(imm_code, code, *opt_flags) {{
40    regs = ['_destRegIdx[0]','_srcRegIdx[0]']
41    iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
42        {'code': code, 'imm_code': imm_code,
43         'regs': ','.join(regs)}, opt_flags)
44    header_output = ImmDeclare.subst(iop)
45    decoder_output = ImmConstructor.subst(iop)
46    decode_block = BasicDecode.subst(iop)
47    exec_output = ImmExecute.subst(iop)
48}};
49
50def format CUIOp(imm_code, code, *opt_flags) {{
51    regs = ['_destRegIdx[0]','_srcRegIdx[0]']
52    iop = InstObjParams(name, Name, 'ImmOp<uint64_t>',
53        {'code': code, 'imm_code': imm_code,
54         'regs': ','.join(regs)}, opt_flags)
55    header_output = ImmDeclare.subst(iop)
56    decoder_output = ImmConstructor.subst(iop)
57    decode_block = BasicDecode.subst(iop)
58    exec_output = ImmExecute.subst(iop)
59}};
60
61def format CompressedLoad(ldisp_code, memacc_code,
62        ea_code, mem_flags=[], inst_flags=[]) {{
63    (header_output, decoder_output, decode_block, exec_output) = \
64        LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags,
65        inst_flags, 'Load', exec_template_base='Load')
66}};
67
68def format CompressedStore(sdisp_code, memacc_code,
69        ea_code, mem_flags=[], inst_flags=[]) {{
70    (header_output, decoder_output, decode_block, exec_output) = \
71        LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags,
72        inst_flags, 'Store', exec_template_base='Store')
73}};