compressed.isa revision 12320:d846aaaa33b1 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are
9// met: redistributions of source code must retain the above copyright
10// notice, this list of conditions and the following disclaimer;
11// redistributions in binary form must reproduce the above copyright
12// notice, this list of conditions and the following disclaimer in the
13// documentation and/or other materials provided with the distribution;
14// neither the name of the copyright holders nor the names of its
15// contributors may be used to endorse or promote products derived from
16// this software without specific prior written permission.
17//
18// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Alec Roelke
31
32output header {{
33    /**
34     * Base class for compressed operations that work only on registers
35     */
36    class CompRegOp : public RiscvStaticInst
37    {
38      protected:
39        /// Constructor
40        CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
41            : RiscvStaticInst(mnem, _machInst, __opClass)
42        {}
43
44        std::string
45        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
46    };
47}};
48
49output decoder {{
50    std::string
51    CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
52    {
53        std::stringstream ss;
54        ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
55            registerName(_srcRegIdx[0]);
56        return ss.str();
57    }
58}};
59
60def format CROp(code, *opt_flags) {{
61    iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
62    header_output = BasicDeclare.subst(iop)
63    decoder_output = BasicConstructor.subst(iop)
64    decode_block = BasicDecode.subst(iop)
65    exec_output = BasicExecute.subst(iop)
66}};
67
68def format CIOp(imm_code, code, *opt_flags) {{
69    regs = ['_destRegIdx[0]','_srcRegIdx[0]']
70    iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
71        {'code': code, 'imm_code': imm_code,
72         'regs': ','.join(regs)}, opt_flags)
73    header_output = ImmDeclare.subst(iop)
74    decoder_output = ImmConstructor.subst(iop)
75    decode_block = BasicDecode.subst(iop)
76    exec_output = ImmExecute.subst(iop)
77}};
78
79def format CUIOp(imm_code, code, *opt_flags) {{
80    regs = ['_destRegIdx[0]','_srcRegIdx[0]']
81    iop = InstObjParams(name, Name, 'ImmOp<uint64_t>',
82        {'code': code, 'imm_code': imm_code,
83         'regs': ','.join(regs)}, opt_flags)
84    header_output = ImmDeclare.subst(iop)
85    decoder_output = ImmConstructor.subst(iop)
86    decode_block = BasicDecode.subst(iop)
87    exec_output = ImmExecute.subst(iop)
88}};
89
90def format CompressedLoad(ldisp_code, memacc_code,
91        ea_code, mem_flags=[], inst_flags=[]) {{
92    (header_output, decoder_output, decode_block, exec_output) = \
93        LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags,
94        inst_flags, 'Load', exec_template_base='Load')
95}};
96
97def format CompressedStore(sdisp_code, memacc_code,
98        ea_code, mem_flags=[], inst_flags=[]) {{
99    (header_output, decoder_output, decode_block, exec_output) = \
100        LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags,
101        inst_flags, 'Store', exec_template_base='Store')
102}};