compressed.isa revision 12120
112120Sar4jc@virginia.edu// -*- mode:c++ -*- 212120Sar4jc@virginia.edu 312120Sar4jc@virginia.edu// Copyright (c) 2015 RISC-V Foundation 412120Sar4jc@virginia.edu// Copyright (c) 2017 The University of Virginia 512120Sar4jc@virginia.edu// All rights reserved. 612120Sar4jc@virginia.edu// 712120Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 812120Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 912120Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 1012120Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 1112120Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 1212120Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 1312120Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 1412120Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 1512120Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 1612120Sar4jc@virginia.edu// this software without specific prior written permission. 1712120Sar4jc@virginia.edu// 1812120Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1912120Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2012120Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2112120Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2212120Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2312120Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2412120Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2512120Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2612120Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2712120Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2812120Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2912120Sar4jc@virginia.edu// 3012120Sar4jc@virginia.edu// Authors: Alec Roelke 3112120Sar4jc@virginia.edu 3212120Sar4jc@virginia.eduoutput header {{ 3312120Sar4jc@virginia.edu /** 3412120Sar4jc@virginia.edu * Base class for compressed operations that work only on registers 3512120Sar4jc@virginia.edu */ 3612120Sar4jc@virginia.edu class CompRegOp : public RiscvStaticInst 3712120Sar4jc@virginia.edu { 3812120Sar4jc@virginia.edu protected: 3912120Sar4jc@virginia.edu /// Constructor 4012120Sar4jc@virginia.edu CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass) 4112120Sar4jc@virginia.edu : RiscvStaticInst(mnem, _machInst, __opClass) 4212120Sar4jc@virginia.edu {} 4312120Sar4jc@virginia.edu 4412120Sar4jc@virginia.edu std::string 4512120Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 4612120Sar4jc@virginia.edu }; 4712120Sar4jc@virginia.edu}}; 4812120Sar4jc@virginia.edu 4912120Sar4jc@virginia.eduoutput decoder {{ 5012120Sar4jc@virginia.edu std::string 5112120Sar4jc@virginia.edu CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 5212120Sar4jc@virginia.edu { 5312120Sar4jc@virginia.edu std::stringstream ss; 5412120Sar4jc@virginia.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << 5512120Sar4jc@virginia.edu registerName(_srcRegIdx[0]); 5612120Sar4jc@virginia.edu return ss.str(); 5712120Sar4jc@virginia.edu } 5812120Sar4jc@virginia.edu}}; 5912120Sar4jc@virginia.edu 6012120Sar4jc@virginia.edudef format CROp(code, *opt_flags) {{ 6112120Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags) 6212120Sar4jc@virginia.edu header_output = BasicDeclare.subst(iop) 6312120Sar4jc@virginia.edu decoder_output = BasicConstructor.subst(iop) 6412120Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 6512120Sar4jc@virginia.edu exec_output = BasicExecute.subst(iop) 6612120Sar4jc@virginia.edu}}; 6712120Sar4jc@virginia.edu 6812120Sar4jc@virginia.edudef format CIOp(imm_code, code, *opt_flags) {{ 6912120Sar4jc@virginia.edu regs = ['_destRegIdx[0]','_srcRegIdx[0]'] 7012120Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'ImmOp', 7112120Sar4jc@virginia.edu {'code': code, 'imm_code': imm_code, 7212120Sar4jc@virginia.edu 'regs': ','.join(regs)}, opt_flags) 7312120Sar4jc@virginia.edu header_output = ImmDeclare.subst(iop) 7412120Sar4jc@virginia.edu decoder_output = ImmConstructor.subst(iop) 7512120Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 7612120Sar4jc@virginia.edu exec_output = ImmExecute.subst(iop) 7712120Sar4jc@virginia.edu}}; 7812120Sar4jc@virginia.edu 7912120Sar4jc@virginia.edudef format CUIOp(imm_code, code, *opt_flags) {{ 8012120Sar4jc@virginia.edu regs = ['_destRegIdx[0]','_srcRegIdx[0]'] 8112120Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'UImmOp', 8212120Sar4jc@virginia.edu {'code': code, 'imm_code': imm_code, 8312120Sar4jc@virginia.edu 'regs': ','.join(regs)}, opt_flags) 8412120Sar4jc@virginia.edu header_output = ImmDeclare.subst(iop) 8512120Sar4jc@virginia.edu decoder_output = ImmConstructor.subst(iop) 8612120Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 8712120Sar4jc@virginia.edu exec_output = ImmExecute.subst(iop) 8812120Sar4jc@virginia.edu}}; 8912120Sar4jc@virginia.edu 9012120Sar4jc@virginia.edudef format CompressedLoad(ldisp_code, memacc_code, 9112120Sar4jc@virginia.edu ea_code, mem_flags=[], inst_flags=[]) {{ 9212120Sar4jc@virginia.edu (header_output, decoder_output, decode_block, exec_output) = \ 9312120Sar4jc@virginia.edu LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags, 9412120Sar4jc@virginia.edu inst_flags, 'Load', exec_template_base='Load') 9512120Sar4jc@virginia.edu}}; 9612120Sar4jc@virginia.edu 9712120Sar4jc@virginia.edudef format CompressedStore(sdisp_code, memacc_code, 9812120Sar4jc@virginia.edu ea_code, mem_flags=[], inst_flags=[]) {{ 9912120Sar4jc@virginia.edu (header_output, decoder_output, decode_block, exec_output) = \ 10012120Sar4jc@virginia.edu LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags, 10112120Sar4jc@virginia.edu inst_flags, 'Store', exec_template_base='Store') 10212120Sar4jc@virginia.edu}};