amo.isa revision 12119
111726Sar4jc@virginia.edu// -*- mode:c++ -*- 211726Sar4jc@virginia.edu 311726Sar4jc@virginia.edu// Copyright (c) 2015 Riscv Developers 411726Sar4jc@virginia.edu// Copyright (c) 2016 The University of Virginia 511726Sar4jc@virginia.edu// All rights reserved. 611726Sar4jc@virginia.edu// 711726Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 811726Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 911726Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 1011726Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 1111726Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 1211726Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 1311726Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 1411726Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 1511726Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 1611726Sar4jc@virginia.edu// this software without specific prior written permission. 1711726Sar4jc@virginia.edu// 1811726Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1911726Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2011726Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2111726Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2211726Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2311726Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2411726Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2511726Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2611726Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2711726Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2811726Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2911726Sar4jc@virginia.edu// 3011726Sar4jc@virginia.edu// Authors: Alec Roelke 3111726Sar4jc@virginia.edu 3211726Sar4jc@virginia.edu//////////////////////////////////////////////////////////////////// 3311726Sar4jc@virginia.edu// 3411726Sar4jc@virginia.edu// Atomic memory operation instructions 3511726Sar4jc@virginia.edu// 3611726Sar4jc@virginia.eduoutput header {{ 3711965Sar4jc@virginia.edu class LoadReserved : public RiscvStaticInst 3811965Sar4jc@virginia.edu { 3911965Sar4jc@virginia.edu protected: 4011965Sar4jc@virginia.edu Request::Flags memAccessFlags; 4111965Sar4jc@virginia.edu 4211965Sar4jc@virginia.edu LoadReserved(const char *mnem, ExtMachInst _machInst, 4311965Sar4jc@virginia.edu OpClass __opClass) 4411965Sar4jc@virginia.edu : RiscvStaticInst(mnem, _machInst, __opClass) 4511965Sar4jc@virginia.edu {} 4611965Sar4jc@virginia.edu 4711965Sar4jc@virginia.edu std::string 4811965Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 4911965Sar4jc@virginia.edu }; 5011965Sar4jc@virginia.edu 5111965Sar4jc@virginia.edu class StoreCond : public RiscvStaticInst 5211965Sar4jc@virginia.edu { 5311965Sar4jc@virginia.edu protected: 5411965Sar4jc@virginia.edu Request::Flags memAccessFlags; 5511965Sar4jc@virginia.edu 5611965Sar4jc@virginia.edu StoreCond(const char* mnem, ExtMachInst _machInst, OpClass __opClass) 5711965Sar4jc@virginia.edu : RiscvStaticInst(mnem, _machInst, __opClass) 5811965Sar4jc@virginia.edu {} 5911965Sar4jc@virginia.edu 6011965Sar4jc@virginia.edu std::string 6111965Sar4jc@virginia.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 6211965Sar4jc@virginia.edu }; 6311965Sar4jc@virginia.edu 6411726Sar4jc@virginia.edu class AtomicMemOp : public RiscvMacroInst 6511726Sar4jc@virginia.edu { 6611726Sar4jc@virginia.edu protected: 6711726Sar4jc@virginia.edu /// Constructor 6811726Sar4jc@virginia.edu // Each AtomicMemOp has a load and a store phase 6911726Sar4jc@virginia.edu AtomicMemOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 7011726Sar4jc@virginia.edu : RiscvMacroInst(mnem, _machInst, __opClass) 7111726Sar4jc@virginia.edu {} 7211726Sar4jc@virginia.edu 7311726Sar4jc@virginia.edu std::string generateDisassembly(Addr pc, 7411726Sar4jc@virginia.edu const SymbolTable *symtab) const; 7511726Sar4jc@virginia.edu }; 7611726Sar4jc@virginia.edu 7711726Sar4jc@virginia.edu class AtomicMemOpMicro : public RiscvMicroInst 7811726Sar4jc@virginia.edu { 7911726Sar4jc@virginia.edu protected: 8011726Sar4jc@virginia.edu /// Memory request flags. See mem/request.hh. 8111726Sar4jc@virginia.edu Request::Flags memAccessFlags; 8211726Sar4jc@virginia.edu 8311726Sar4jc@virginia.edu /// Constructor 8411726Sar4jc@virginia.edu AtomicMemOpMicro(const char *mnem, ExtMachInst _machInst, 8511726Sar4jc@virginia.edu OpClass __opClass) 8611726Sar4jc@virginia.edu : RiscvMicroInst(mnem, _machInst, __opClass) 8711726Sar4jc@virginia.edu {} 8811726Sar4jc@virginia.edu 8911726Sar4jc@virginia.edu std::string generateDisassembly(Addr pc, 9011726Sar4jc@virginia.edu const SymbolTable *symtab) const; 9111726Sar4jc@virginia.edu }; 9211726Sar4jc@virginia.edu}}; 9311726Sar4jc@virginia.edu 9411726Sar4jc@virginia.eduoutput decoder {{ 9511965Sar4jc@virginia.edu std::string LoadReserved::generateDisassembly(Addr pc, 9611965Sar4jc@virginia.edu const SymbolTable *symtab) const 9711965Sar4jc@virginia.edu { 9811965Sar4jc@virginia.edu std::stringstream ss; 9912119Sar4jc@virginia.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", (" 10012119Sar4jc@virginia.edu << registerName(_srcRegIdx[0]) << ')'; 10111965Sar4jc@virginia.edu return ss.str(); 10211965Sar4jc@virginia.edu } 10311965Sar4jc@virginia.edu 10411965Sar4jc@virginia.edu std::string StoreCond::generateDisassembly(Addr pc, 10511965Sar4jc@virginia.edu const SymbolTable *symtab) const 10611965Sar4jc@virginia.edu { 10711965Sar4jc@virginia.edu std::stringstream ss; 10812119Sar4jc@virginia.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 10912119Sar4jc@virginia.edu << registerName(_srcRegIdx[1]) << ", (" 11012119Sar4jc@virginia.edu << registerName(_srcRegIdx[0]) << ')'; 11111965Sar4jc@virginia.edu return ss.str(); 11211965Sar4jc@virginia.edu } 11311965Sar4jc@virginia.edu 11411726Sar4jc@virginia.edu std::string AtomicMemOp::generateDisassembly(Addr pc, 11511726Sar4jc@virginia.edu const SymbolTable *symtab) const 11611726Sar4jc@virginia.edu { 11711726Sar4jc@virginia.edu std::stringstream ss; 11812119Sar4jc@virginia.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 11912119Sar4jc@virginia.edu << registerName(_srcRegIdx[1]) << ", (" 12012119Sar4jc@virginia.edu << registerName(_srcRegIdx[0]) << ')'; 12111726Sar4jc@virginia.edu return ss.str(); 12211726Sar4jc@virginia.edu } 12311726Sar4jc@virginia.edu 12411726Sar4jc@virginia.edu std::string AtomicMemOpMicro::generateDisassembly(Addr pc, 12511726Sar4jc@virginia.edu const SymbolTable *symtab) const 12611726Sar4jc@virginia.edu { 12711726Sar4jc@virginia.edu std::stringstream ss; 12811726Sar4jc@virginia.edu ss << csprintf("0x%08x", machInst) << ' ' << mnemonic; 12911726Sar4jc@virginia.edu return ss.str(); 13011726Sar4jc@virginia.edu } 13111726Sar4jc@virginia.edu}}; 13211726Sar4jc@virginia.edu 13311726Sar4jc@virginia.edudef template AtomicMemOpDeclare {{ 13411726Sar4jc@virginia.edu /** 13511726Sar4jc@virginia.edu * Static instruction class for an AtomicMemOp operation 13611726Sar4jc@virginia.edu */ 13711726Sar4jc@virginia.edu class %(class_name)s : public %(base_class)s 13811726Sar4jc@virginia.edu { 13911726Sar4jc@virginia.edu public: 14011726Sar4jc@virginia.edu // Constructor 14111726Sar4jc@virginia.edu %(class_name)s(ExtMachInst machInst); 14211726Sar4jc@virginia.edu 14311726Sar4jc@virginia.edu protected: 14411726Sar4jc@virginia.edu 14511726Sar4jc@virginia.edu class %(class_name)sLoad : public %(base_class)sMicro 14611726Sar4jc@virginia.edu { 14711726Sar4jc@virginia.edu public: 14811726Sar4jc@virginia.edu // Constructor 14911726Sar4jc@virginia.edu %(class_name)sLoad(ExtMachInst machInst, %(class_name)s *_p); 15011726Sar4jc@virginia.edu 15111726Sar4jc@virginia.edu %(BasicExecDeclare)s 15211726Sar4jc@virginia.edu 15311726Sar4jc@virginia.edu %(EACompDeclare)s 15411726Sar4jc@virginia.edu 15511726Sar4jc@virginia.edu %(InitiateAccDeclare)s 15611726Sar4jc@virginia.edu 15711726Sar4jc@virginia.edu %(CompleteAccDeclare)s 15811726Sar4jc@virginia.edu }; 15911726Sar4jc@virginia.edu 16011726Sar4jc@virginia.edu class %(class_name)sStore : public %(base_class)sMicro 16111726Sar4jc@virginia.edu { 16211726Sar4jc@virginia.edu public: 16311726Sar4jc@virginia.edu // Constructor 16411726Sar4jc@virginia.edu %(class_name)sStore(ExtMachInst machInst, %(class_name)s *_p); 16511726Sar4jc@virginia.edu 16611726Sar4jc@virginia.edu %(BasicExecDeclare)s 16711726Sar4jc@virginia.edu 16811726Sar4jc@virginia.edu %(EACompDeclare)s 16911726Sar4jc@virginia.edu 17011726Sar4jc@virginia.edu %(InitiateAccDeclare)s 17111726Sar4jc@virginia.edu 17211726Sar4jc@virginia.edu %(CompleteAccDeclare)s 17311726Sar4jc@virginia.edu }; 17411726Sar4jc@virginia.edu }; 17511726Sar4jc@virginia.edu}}; 17611726Sar4jc@virginia.edu 17711965Sar4jc@virginia.edudef template LRSCConstructor {{ 17811965Sar4jc@virginia.edu %(class_name)s::%(class_name)s(ExtMachInst machInst): 17911965Sar4jc@virginia.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 18011965Sar4jc@virginia.edu { 18111965Sar4jc@virginia.edu %(constructor)s; 18211965Sar4jc@virginia.edu if (AQ) 18311965Sar4jc@virginia.edu memAccessFlags = memAccessFlags | Request::ACQUIRE; 18411965Sar4jc@virginia.edu if (RL) 18511965Sar4jc@virginia.edu memAccessFlags = memAccessFlags | Request::RELEASE; 18611965Sar4jc@virginia.edu } 18711965Sar4jc@virginia.edu}}; 18811965Sar4jc@virginia.edu 18911726Sar4jc@virginia.edudef template AtomicMemOpMacroConstructor {{ 19011726Sar4jc@virginia.edu %(class_name)s::%(class_name)s(ExtMachInst machInst) 19111726Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 19211726Sar4jc@virginia.edu { 19311726Sar4jc@virginia.edu %(constructor)s; 19411726Sar4jc@virginia.edu microops = {new %(class_name)sLoad(machInst, this), 19511726Sar4jc@virginia.edu new %(class_name)sStore(machInst, this)}; 19611726Sar4jc@virginia.edu } 19711726Sar4jc@virginia.edu}}; 19811726Sar4jc@virginia.edu 19911726Sar4jc@virginia.edudef template AtomicMemOpLoadConstructor {{ 20011726Sar4jc@virginia.edu %(class_name)s::%(class_name)sLoad::%(class_name)sLoad( 20111726Sar4jc@virginia.edu ExtMachInst machInst, %(class_name)s *_p) 20211726Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s[l]", machInst, %(op_class)s) 20311726Sar4jc@virginia.edu { 20411726Sar4jc@virginia.edu %(constructor)s; 20511726Sar4jc@virginia.edu flags[IsFirstMicroop] = true; 20611726Sar4jc@virginia.edu flags[IsDelayedCommit] = true; 20711726Sar4jc@virginia.edu if (AQ) 20811726Sar4jc@virginia.edu memAccessFlags = Request::ACQUIRE; 20911726Sar4jc@virginia.edu } 21011726Sar4jc@virginia.edu}}; 21111726Sar4jc@virginia.edu 21211726Sar4jc@virginia.edudef template AtomicMemOpStoreConstructor {{ 21311726Sar4jc@virginia.edu %(class_name)s::%(class_name)sStore::%(class_name)sStore( 21411726Sar4jc@virginia.edu ExtMachInst machInst, %(class_name)s *_p) 21511726Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s[s]", machInst, %(op_class)s) 21611726Sar4jc@virginia.edu { 21711726Sar4jc@virginia.edu %(constructor)s; 21811726Sar4jc@virginia.edu flags[IsLastMicroop] = true; 21911726Sar4jc@virginia.edu flags[IsNonSpeculative] = true; 22011726Sar4jc@virginia.edu if (RL) 22111726Sar4jc@virginia.edu memAccessFlags = Request::RELEASE; 22211726Sar4jc@virginia.edu } 22311726Sar4jc@virginia.edu}}; 22411726Sar4jc@virginia.edu 22511965Sar4jc@virginia.edudef template StoreCondExecute {{ 22611965Sar4jc@virginia.edu Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 22711965Sar4jc@virginia.edu Trace::InstRecord *traceData) const 22811965Sar4jc@virginia.edu { 22911965Sar4jc@virginia.edu Addr EA; 23011965Sar4jc@virginia.edu Fault fault = NoFault; 23111965Sar4jc@virginia.edu uint64_t result; 23211965Sar4jc@virginia.edu 23311965Sar4jc@virginia.edu %(op_decl)s; 23411965Sar4jc@virginia.edu %(op_rd)s; 23511965Sar4jc@virginia.edu %(ea_code)s; 23611965Sar4jc@virginia.edu 23711965Sar4jc@virginia.edu if (fault == NoFault) { 23811965Sar4jc@virginia.edu %(memacc_code)s; 23911965Sar4jc@virginia.edu } 24011965Sar4jc@virginia.edu 24111965Sar4jc@virginia.edu if (fault == NoFault) { 24211965Sar4jc@virginia.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 24311965Sar4jc@virginia.edu &result); 24411965Sar4jc@virginia.edu // RISC-V has the opposite convention gem5 has for success flags, 24511965Sar4jc@virginia.edu // so we invert the result here. 24611965Sar4jc@virginia.edu result = !result; 24711965Sar4jc@virginia.edu } 24811965Sar4jc@virginia.edu 24911965Sar4jc@virginia.edu if (fault == NoFault) { 25011965Sar4jc@virginia.edu %(postacc_code)s; 25111965Sar4jc@virginia.edu } 25211965Sar4jc@virginia.edu 25311965Sar4jc@virginia.edu if (fault == NoFault) { 25411965Sar4jc@virginia.edu %(op_wb)s; 25511965Sar4jc@virginia.edu } 25611965Sar4jc@virginia.edu 25711965Sar4jc@virginia.edu return fault; 25811965Sar4jc@virginia.edu } 25911965Sar4jc@virginia.edu}}; 26011965Sar4jc@virginia.edu 26111726Sar4jc@virginia.edudef template AtomicMemOpLoadExecute {{ 26211726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sLoad::execute(CPU_EXEC_CONTEXT *xc, 26311726Sar4jc@virginia.edu Trace::InstRecord *traceData) const 26411726Sar4jc@virginia.edu { 26511726Sar4jc@virginia.edu Addr EA; 26611726Sar4jc@virginia.edu Fault fault = NoFault; 26711726Sar4jc@virginia.edu 26811726Sar4jc@virginia.edu %(op_decl)s; 26911726Sar4jc@virginia.edu %(op_rd)s; 27011726Sar4jc@virginia.edu %(ea_code)s; 27111726Sar4jc@virginia.edu 27211726Sar4jc@virginia.edu if (fault == NoFault) { 27311726Sar4jc@virginia.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 27411726Sar4jc@virginia.edu } 27511726Sar4jc@virginia.edu 27611726Sar4jc@virginia.edu if (fault == NoFault) { 27711726Sar4jc@virginia.edu %(code)s; 27811726Sar4jc@virginia.edu } 27911726Sar4jc@virginia.edu 28011726Sar4jc@virginia.edu if (fault == NoFault) { 28111726Sar4jc@virginia.edu %(op_wb)s; 28211726Sar4jc@virginia.edu } 28311726Sar4jc@virginia.edu 28411726Sar4jc@virginia.edu return fault; 28511726Sar4jc@virginia.edu } 28611726Sar4jc@virginia.edu}}; 28711726Sar4jc@virginia.edu 28811726Sar4jc@virginia.edudef template AtomicMemOpStoreExecute {{ 28911726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sStore::execute(CPU_EXEC_CONTEXT *xc, 29011726Sar4jc@virginia.edu Trace::InstRecord *traceData) const 29111726Sar4jc@virginia.edu { 29211726Sar4jc@virginia.edu Addr EA; 29311726Sar4jc@virginia.edu Fault fault = NoFault; 29411726Sar4jc@virginia.edu 29511726Sar4jc@virginia.edu %(op_decl)s; 29611726Sar4jc@virginia.edu %(op_rd)s; 29711726Sar4jc@virginia.edu %(ea_code)s; 29811726Sar4jc@virginia.edu 29911726Sar4jc@virginia.edu if (fault == NoFault) { 30011726Sar4jc@virginia.edu %(code)s; 30111726Sar4jc@virginia.edu } 30211726Sar4jc@virginia.edu 30311726Sar4jc@virginia.edu if (fault == NoFault) { 30411726Sar4jc@virginia.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 30511726Sar4jc@virginia.edu nullptr); 30611726Sar4jc@virginia.edu } 30711726Sar4jc@virginia.edu 30811726Sar4jc@virginia.edu if (fault == NoFault) { 30911726Sar4jc@virginia.edu %(op_wb)s; 31011726Sar4jc@virginia.edu } 31111726Sar4jc@virginia.edu 31211726Sar4jc@virginia.edu return fault; 31311726Sar4jc@virginia.edu } 31411726Sar4jc@virginia.edu}}; 31511726Sar4jc@virginia.edu 31612119Sar4jc@virginia.edudef template AtomicMemOpEACompExecute {{ 31711965Sar4jc@virginia.edu Fault 31812119Sar4jc@virginia.edu %(class_name)s::%(class_name)s%(op_name)s::eaComp(CPU_EXEC_CONTEXT *xc, 31911965Sar4jc@virginia.edu Trace::InstRecord *traceData) const 32011965Sar4jc@virginia.edu { 32111965Sar4jc@virginia.edu Addr EA; 32211965Sar4jc@virginia.edu Fault fault = NoFault; 32311965Sar4jc@virginia.edu 32411965Sar4jc@virginia.edu %(op_decl)s; 32511965Sar4jc@virginia.edu %(op_rd)s; 32611965Sar4jc@virginia.edu %(ea_code)s; 32711965Sar4jc@virginia.edu 32811965Sar4jc@virginia.edu if (fault == NoFault) { 32911965Sar4jc@virginia.edu %(op_wb)s; 33011965Sar4jc@virginia.edu xc->setEA(EA); 33111965Sar4jc@virginia.edu } 33211965Sar4jc@virginia.edu 33311965Sar4jc@virginia.edu return fault; 33411965Sar4jc@virginia.edu } 33511965Sar4jc@virginia.edu}}; 33611965Sar4jc@virginia.edu 33711726Sar4jc@virginia.edudef template AtomicMemOpLoadInitiateAcc {{ 33811726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sLoad::initiateAcc(CPU_EXEC_CONTEXT *xc, 33911726Sar4jc@virginia.edu Trace::InstRecord *traceData) const 34011726Sar4jc@virginia.edu { 34111726Sar4jc@virginia.edu Addr EA; 34211726Sar4jc@virginia.edu Fault fault = NoFault; 34311726Sar4jc@virginia.edu 34411726Sar4jc@virginia.edu %(op_src_decl)s; 34511726Sar4jc@virginia.edu %(op_rd)s; 34611726Sar4jc@virginia.edu %(ea_code)s; 34711726Sar4jc@virginia.edu 34811726Sar4jc@virginia.edu if (fault == NoFault) { 34911726Sar4jc@virginia.edu fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); 35011726Sar4jc@virginia.edu } 35111726Sar4jc@virginia.edu 35211726Sar4jc@virginia.edu return fault; 35311726Sar4jc@virginia.edu } 35411726Sar4jc@virginia.edu}}; 35511726Sar4jc@virginia.edu 35611726Sar4jc@virginia.edudef template AtomicMemOpStoreInitiateAcc {{ 35711726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sStore::initiateAcc( 35811726Sar4jc@virginia.edu CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 35911726Sar4jc@virginia.edu { 36011726Sar4jc@virginia.edu Addr EA; 36111726Sar4jc@virginia.edu Fault fault = NoFault; 36211726Sar4jc@virginia.edu 36311726Sar4jc@virginia.edu %(op_decl)s; 36411726Sar4jc@virginia.edu %(op_rd)s; 36511726Sar4jc@virginia.edu %(ea_code)s; 36611726Sar4jc@virginia.edu 36711726Sar4jc@virginia.edu if (fault == NoFault) { 36811726Sar4jc@virginia.edu %(code)s; 36911726Sar4jc@virginia.edu } 37011726Sar4jc@virginia.edu 37111726Sar4jc@virginia.edu if (fault == NoFault) { 37211726Sar4jc@virginia.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 37311726Sar4jc@virginia.edu nullptr); 37411726Sar4jc@virginia.edu } 37511726Sar4jc@virginia.edu 37611726Sar4jc@virginia.edu if (fault == NoFault) { 37711726Sar4jc@virginia.edu %(op_wb)s; 37811726Sar4jc@virginia.edu } 37911726Sar4jc@virginia.edu 38011726Sar4jc@virginia.edu return fault; 38111726Sar4jc@virginia.edu } 38211726Sar4jc@virginia.edu}}; 38311726Sar4jc@virginia.edu 38411965Sar4jc@virginia.edudef template StoreCondCompleteAcc {{ 38511965Sar4jc@virginia.edu Fault %(class_name)s::completeAcc(Packet *pkt, CPU_EXEC_CONTEXT *xc, 38611965Sar4jc@virginia.edu Trace::InstRecord *traceData) const 38711965Sar4jc@virginia.edu { 38811965Sar4jc@virginia.edu Fault fault = NoFault; 38911965Sar4jc@virginia.edu 39011965Sar4jc@virginia.edu %(op_dest_decl)s; 39111965Sar4jc@virginia.edu 39211965Sar4jc@virginia.edu // RISC-V has the opposite convention gem5 has for success flags, 39311965Sar4jc@virginia.edu // so we invert the result here. 39411965Sar4jc@virginia.edu uint64_t result = !pkt->req->getExtraData(); 39511965Sar4jc@virginia.edu 39611965Sar4jc@virginia.edu if (fault == NoFault) { 39711965Sar4jc@virginia.edu %(postacc_code)s; 39811965Sar4jc@virginia.edu } 39911965Sar4jc@virginia.edu 40011965Sar4jc@virginia.edu if (fault == NoFault) { 40111965Sar4jc@virginia.edu %(op_wb)s; 40211965Sar4jc@virginia.edu } 40311965Sar4jc@virginia.edu 40411965Sar4jc@virginia.edu return fault; 40511965Sar4jc@virginia.edu } 40611965Sar4jc@virginia.edu}}; 40711965Sar4jc@virginia.edu 40811726Sar4jc@virginia.edudef template AtomicMemOpLoadCompleteAcc {{ 40911726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sLoad::completeAcc(PacketPtr pkt, 41011726Sar4jc@virginia.edu CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 41111726Sar4jc@virginia.edu { 41211726Sar4jc@virginia.edu Fault fault = NoFault; 41311726Sar4jc@virginia.edu 41411726Sar4jc@virginia.edu %(op_decl)s; 41511726Sar4jc@virginia.edu %(op_rd)s; 41611726Sar4jc@virginia.edu 41711726Sar4jc@virginia.edu getMem(pkt, Mem, traceData); 41811726Sar4jc@virginia.edu 41911726Sar4jc@virginia.edu if (fault == NoFault) { 42011726Sar4jc@virginia.edu %(code)s; 42111726Sar4jc@virginia.edu } 42211726Sar4jc@virginia.edu 42311726Sar4jc@virginia.edu if (fault == NoFault) { 42411726Sar4jc@virginia.edu %(op_wb)s; 42511726Sar4jc@virginia.edu } 42611726Sar4jc@virginia.edu 42711726Sar4jc@virginia.edu return fault; 42811726Sar4jc@virginia.edu } 42911726Sar4jc@virginia.edu}}; 43011726Sar4jc@virginia.edu 43111726Sar4jc@virginia.edudef template AtomicMemOpStoreCompleteAcc {{ 43211726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sStore::completeAcc(PacketPtr pkt, 43311726Sar4jc@virginia.edu CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 43411726Sar4jc@virginia.edu { 43511726Sar4jc@virginia.edu return NoFault; 43611726Sar4jc@virginia.edu } 43711726Sar4jc@virginia.edu}}; 43811726Sar4jc@virginia.edu 43911965Sar4jc@virginia.edudef format LoadReserved(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}}, 44011965Sar4jc@virginia.edu mem_flags=[], inst_flags=[]) {{ 44111965Sar4jc@virginia.edu mem_flags = makeList(mem_flags) 44211965Sar4jc@virginia.edu inst_flags = makeList(inst_flags) 44311965Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'LoadReserved', 44411965Sar4jc@virginia.edu {'ea_code': ea_code, 'memacc_code': memacc_code, 44511965Sar4jc@virginia.edu 'postacc_code': postacc_code}, inst_flags) 44611965Sar4jc@virginia.edu iop.constructor += '\n\tmemAccessFlags = memAccessFlags | ' + \ 44711965Sar4jc@virginia.edu '|'.join(['Request::%s' % flag for flag in mem_flags]) + ';' 44811965Sar4jc@virginia.edu 44912119Sar4jc@virginia.edu header_output = LoadStoreDeclare.subst(iop) 45011965Sar4jc@virginia.edu decoder_output = LRSCConstructor.subst(iop) 45111965Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 45212119Sar4jc@virginia.edu exec_output = LoadExecute.subst(iop) \ 45312119Sar4jc@virginia.edu + EACompExecute.subst(iop) \ 45412119Sar4jc@virginia.edu + LoadInitiateAcc.subst(iop) \ 45512119Sar4jc@virginia.edu + LoadCompleteAcc.subst(iop) 45611965Sar4jc@virginia.edu}}; 45711965Sar4jc@virginia.edu 45811965Sar4jc@virginia.edudef format StoreCond(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}}, 45911965Sar4jc@virginia.edu mem_flags=[], inst_flags=[]) {{ 46011965Sar4jc@virginia.edu mem_flags = makeList(mem_flags) 46111965Sar4jc@virginia.edu inst_flags = makeList(inst_flags) 46211965Sar4jc@virginia.edu iop = InstObjParams(name, Name, 'StoreCond', 46311965Sar4jc@virginia.edu {'ea_code': ea_code, 'memacc_code': memacc_code, 46411965Sar4jc@virginia.edu 'postacc_code': postacc_code}, inst_flags) 46511965Sar4jc@virginia.edu iop.constructor += '\n\tmemAccessFlags = memAccessFlags | ' + \ 46611965Sar4jc@virginia.edu '|'.join(['Request::%s' % flag for flag in mem_flags]) + ';' 46711965Sar4jc@virginia.edu 46812119Sar4jc@virginia.edu header_output = LoadStoreDeclare.subst(iop) 46911965Sar4jc@virginia.edu decoder_output = LRSCConstructor.subst(iop) 47011965Sar4jc@virginia.edu decode_block = BasicDecode.subst(iop) 47111965Sar4jc@virginia.edu exec_output = StoreCondExecute.subst(iop) \ 47212119Sar4jc@virginia.edu + EACompExecute.subst(iop) \ 47312119Sar4jc@virginia.edu + StoreInitiateAcc.subst(iop) \ 47411965Sar4jc@virginia.edu + StoreCondCompleteAcc.subst(iop) 47511965Sar4jc@virginia.edu}}; 47611965Sar4jc@virginia.edu 47711726Sar4jc@virginia.edudef format AtomicMemOp(load_code, store_code, ea_code, load_flags=[], 47811726Sar4jc@virginia.edu store_flags=[], inst_flags=[]) {{ 47911726Sar4jc@virginia.edu macro_iop = InstObjParams(name, Name, 'AtomicMemOp', ea_code, inst_flags) 48011726Sar4jc@virginia.edu header_output = AtomicMemOpDeclare.subst(macro_iop) 48111726Sar4jc@virginia.edu decoder_output = AtomicMemOpMacroConstructor.subst(macro_iop) 48212119Sar4jc@virginia.edu decode_block = BasicDecode.subst(macro_iop) 48311726Sar4jc@virginia.edu exec_output = '' 48411726Sar4jc@virginia.edu 48511726Sar4jc@virginia.edu load_inst_flags = makeList(inst_flags) + ["IsMemRef", "IsLoad"] 48611726Sar4jc@virginia.edu load_iop = InstObjParams(name, Name, 'AtomicMemOpMicro', 48712119Sar4jc@virginia.edu {'ea_code': ea_code, 'code': load_code, 'op_name': 'Load'}, 48812119Sar4jc@virginia.edu load_inst_flags) 48911726Sar4jc@virginia.edu decoder_output += AtomicMemOpLoadConstructor.subst(load_iop) 49011726Sar4jc@virginia.edu exec_output += AtomicMemOpLoadExecute.subst(load_iop) \ 49112119Sar4jc@virginia.edu + AtomicMemOpEACompExecute.subst(load_iop) \ 49211726Sar4jc@virginia.edu + AtomicMemOpLoadInitiateAcc.subst(load_iop) \ 49311726Sar4jc@virginia.edu + AtomicMemOpLoadCompleteAcc.subst(load_iop) 49411726Sar4jc@virginia.edu 49511726Sar4jc@virginia.edu store_inst_flags = makeList(inst_flags) + ["IsMemRef", "IsStore"] 49611726Sar4jc@virginia.edu store_iop = InstObjParams(name, Name, 'AtomicMemOpMicro', 49712119Sar4jc@virginia.edu {'ea_code': ea_code, 'code': store_code, 'op_name': 'Store'}, 49812119Sar4jc@virginia.edu store_inst_flags) 49911726Sar4jc@virginia.edu decoder_output += AtomicMemOpStoreConstructor.subst(store_iop) 50011726Sar4jc@virginia.edu exec_output += AtomicMemOpStoreExecute.subst(store_iop) \ 50112119Sar4jc@virginia.edu + AtomicMemOpEACompExecute.subst(store_iop) \ 50211726Sar4jc@virginia.edu + AtomicMemOpStoreInitiateAcc.subst(store_iop) \ 50311726Sar4jc@virginia.edu + AtomicMemOpStoreCompleteAcc.subst(store_iop) 50411726Sar4jc@virginia.edu}}; 505