amo.isa revision 11726
111726Sar4jc@virginia.edu// -*- mode:c++ -*- 211726Sar4jc@virginia.edu 311726Sar4jc@virginia.edu// Copyright (c) 2015 Riscv Developers 411726Sar4jc@virginia.edu// Copyright (c) 2016 The University of Virginia 511726Sar4jc@virginia.edu// All rights reserved. 611726Sar4jc@virginia.edu// 711726Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 811726Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 911726Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 1011726Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 1111726Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 1211726Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 1311726Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 1411726Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 1511726Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 1611726Sar4jc@virginia.edu// this software without specific prior written permission. 1711726Sar4jc@virginia.edu// 1811726Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1911726Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2011726Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2111726Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2211726Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2311726Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2411726Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2511726Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2611726Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2711726Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2811726Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2911726Sar4jc@virginia.edu// 3011726Sar4jc@virginia.edu// Authors: Alec Roelke 3111726Sar4jc@virginia.edu 3211726Sar4jc@virginia.edu//////////////////////////////////////////////////////////////////// 3311726Sar4jc@virginia.edu// 3411726Sar4jc@virginia.edu// Atomic memory operation instructions 3511726Sar4jc@virginia.edu// 3611726Sar4jc@virginia.eduoutput header {{ 3711726Sar4jc@virginia.edu class AtomicMemOp : public RiscvMacroInst 3811726Sar4jc@virginia.edu { 3911726Sar4jc@virginia.edu protected: 4011726Sar4jc@virginia.edu /// Constructor 4111726Sar4jc@virginia.edu // Each AtomicMemOp has a load and a store phase 4211726Sar4jc@virginia.edu AtomicMemOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 4311726Sar4jc@virginia.edu : RiscvMacroInst(mnem, _machInst, __opClass) 4411726Sar4jc@virginia.edu {} 4511726Sar4jc@virginia.edu 4611726Sar4jc@virginia.edu std::string generateDisassembly(Addr pc, 4711726Sar4jc@virginia.edu const SymbolTable *symtab) const; 4811726Sar4jc@virginia.edu }; 4911726Sar4jc@virginia.edu 5011726Sar4jc@virginia.edu class AtomicMemOpMicro : public RiscvMicroInst 5111726Sar4jc@virginia.edu { 5211726Sar4jc@virginia.edu protected: 5311726Sar4jc@virginia.edu /// Memory request flags. See mem/request.hh. 5411726Sar4jc@virginia.edu Request::Flags memAccessFlags; 5511726Sar4jc@virginia.edu 5611726Sar4jc@virginia.edu /// Constructor 5711726Sar4jc@virginia.edu AtomicMemOpMicro(const char *mnem, ExtMachInst _machInst, 5811726Sar4jc@virginia.edu OpClass __opClass) 5911726Sar4jc@virginia.edu : RiscvMicroInst(mnem, _machInst, __opClass) 6011726Sar4jc@virginia.edu {} 6111726Sar4jc@virginia.edu 6211726Sar4jc@virginia.edu std::string generateDisassembly(Addr pc, 6311726Sar4jc@virginia.edu const SymbolTable *symtab) const; 6411726Sar4jc@virginia.edu }; 6511726Sar4jc@virginia.edu}}; 6611726Sar4jc@virginia.edu 6711726Sar4jc@virginia.eduoutput decoder {{ 6811726Sar4jc@virginia.edu std::string AtomicMemOp::generateDisassembly(Addr pc, 6911726Sar4jc@virginia.edu const SymbolTable *symtab) const 7011726Sar4jc@virginia.edu { 7111726Sar4jc@virginia.edu std::stringstream ss; 7211726Sar4jc@virginia.edu ss << csprintf("0x%08x", machInst) << ' '; 7311726Sar4jc@virginia.edu ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " 7411726Sar4jc@virginia.edu << regName(_srcRegIdx[1]) << ", (" 7511726Sar4jc@virginia.edu << regName(_srcRegIdx[0]) << ')'; 7611726Sar4jc@virginia.edu return ss.str(); 7711726Sar4jc@virginia.edu } 7811726Sar4jc@virginia.edu 7911726Sar4jc@virginia.edu std::string AtomicMemOpMicro::generateDisassembly(Addr pc, 8011726Sar4jc@virginia.edu const SymbolTable *symtab) const 8111726Sar4jc@virginia.edu { 8211726Sar4jc@virginia.edu std::stringstream ss; 8311726Sar4jc@virginia.edu ss << csprintf("0x%08x", machInst) << ' ' << mnemonic; 8411726Sar4jc@virginia.edu return ss.str(); 8511726Sar4jc@virginia.edu } 8611726Sar4jc@virginia.edu}}; 8711726Sar4jc@virginia.edu 8811726Sar4jc@virginia.edudef template AtomicMemOpDeclare {{ 8911726Sar4jc@virginia.edu /** 9011726Sar4jc@virginia.edu * Static instruction class for an AtomicMemOp operation 9111726Sar4jc@virginia.edu */ 9211726Sar4jc@virginia.edu class %(class_name)s : public %(base_class)s 9311726Sar4jc@virginia.edu { 9411726Sar4jc@virginia.edu public: 9511726Sar4jc@virginia.edu // Constructor 9611726Sar4jc@virginia.edu %(class_name)s(ExtMachInst machInst); 9711726Sar4jc@virginia.edu 9811726Sar4jc@virginia.edu protected: 9911726Sar4jc@virginia.edu 10011726Sar4jc@virginia.edu class %(class_name)sLoad : public %(base_class)sMicro 10111726Sar4jc@virginia.edu { 10211726Sar4jc@virginia.edu public: 10311726Sar4jc@virginia.edu // Constructor 10411726Sar4jc@virginia.edu %(class_name)sLoad(ExtMachInst machInst, %(class_name)s *_p); 10511726Sar4jc@virginia.edu 10611726Sar4jc@virginia.edu %(BasicExecDeclare)s 10711726Sar4jc@virginia.edu 10811726Sar4jc@virginia.edu %(EACompDeclare)s 10911726Sar4jc@virginia.edu 11011726Sar4jc@virginia.edu %(InitiateAccDeclare)s 11111726Sar4jc@virginia.edu 11211726Sar4jc@virginia.edu %(CompleteAccDeclare)s 11311726Sar4jc@virginia.edu }; 11411726Sar4jc@virginia.edu 11511726Sar4jc@virginia.edu class %(class_name)sStore : public %(base_class)sMicro 11611726Sar4jc@virginia.edu { 11711726Sar4jc@virginia.edu public: 11811726Sar4jc@virginia.edu // Constructor 11911726Sar4jc@virginia.edu %(class_name)sStore(ExtMachInst machInst, %(class_name)s *_p); 12011726Sar4jc@virginia.edu 12111726Sar4jc@virginia.edu %(BasicExecDeclare)s 12211726Sar4jc@virginia.edu 12311726Sar4jc@virginia.edu %(EACompDeclare)s 12411726Sar4jc@virginia.edu 12511726Sar4jc@virginia.edu %(InitiateAccDeclare)s 12611726Sar4jc@virginia.edu 12711726Sar4jc@virginia.edu %(CompleteAccDeclare)s 12811726Sar4jc@virginia.edu }; 12911726Sar4jc@virginia.edu }; 13011726Sar4jc@virginia.edu}}; 13111726Sar4jc@virginia.edu 13211726Sar4jc@virginia.edudef template AtomicMemOpMacroConstructor {{ 13311726Sar4jc@virginia.edu %(class_name)s::%(class_name)s(ExtMachInst machInst) 13411726Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 13511726Sar4jc@virginia.edu { 13611726Sar4jc@virginia.edu %(constructor)s; 13711726Sar4jc@virginia.edu microops = {new %(class_name)sLoad(machInst, this), 13811726Sar4jc@virginia.edu new %(class_name)sStore(machInst, this)}; 13911726Sar4jc@virginia.edu } 14011726Sar4jc@virginia.edu}}; 14111726Sar4jc@virginia.edu 14211726Sar4jc@virginia.edudef template AtomicMemOpLoadConstructor {{ 14311726Sar4jc@virginia.edu %(class_name)s::%(class_name)sLoad::%(class_name)sLoad( 14411726Sar4jc@virginia.edu ExtMachInst machInst, %(class_name)s *_p) 14511726Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s[l]", machInst, %(op_class)s) 14611726Sar4jc@virginia.edu { 14711726Sar4jc@virginia.edu %(constructor)s; 14811726Sar4jc@virginia.edu flags[IsFirstMicroop] = true; 14911726Sar4jc@virginia.edu flags[IsDelayedCommit] = true; 15011726Sar4jc@virginia.edu if (AQ) 15111726Sar4jc@virginia.edu memAccessFlags = Request::ACQUIRE; 15211726Sar4jc@virginia.edu } 15311726Sar4jc@virginia.edu}}; 15411726Sar4jc@virginia.edu 15511726Sar4jc@virginia.edudef template AtomicMemOpStoreConstructor {{ 15611726Sar4jc@virginia.edu %(class_name)s::%(class_name)sStore::%(class_name)sStore( 15711726Sar4jc@virginia.edu ExtMachInst machInst, %(class_name)s *_p) 15811726Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s[s]", machInst, %(op_class)s) 15911726Sar4jc@virginia.edu { 16011726Sar4jc@virginia.edu %(constructor)s; 16111726Sar4jc@virginia.edu flags[IsLastMicroop] = true; 16211726Sar4jc@virginia.edu flags[IsNonSpeculative] = true; 16311726Sar4jc@virginia.edu if (RL) 16411726Sar4jc@virginia.edu memAccessFlags = Request::RELEASE; 16511726Sar4jc@virginia.edu } 16611726Sar4jc@virginia.edu}}; 16711726Sar4jc@virginia.edu 16811726Sar4jc@virginia.edudef template AtomicMemOpMacroDecode {{ 16911726Sar4jc@virginia.edu return new %(class_name)s(machInst); 17011726Sar4jc@virginia.edu}}; 17111726Sar4jc@virginia.edu 17211726Sar4jc@virginia.edudef template AtomicMemOpLoadExecute {{ 17311726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sLoad::execute(CPU_EXEC_CONTEXT *xc, 17411726Sar4jc@virginia.edu Trace::InstRecord *traceData) const 17511726Sar4jc@virginia.edu { 17611726Sar4jc@virginia.edu Addr EA; 17711726Sar4jc@virginia.edu Fault fault = NoFault; 17811726Sar4jc@virginia.edu 17911726Sar4jc@virginia.edu %(op_decl)s; 18011726Sar4jc@virginia.edu %(op_rd)s; 18111726Sar4jc@virginia.edu %(ea_code)s; 18211726Sar4jc@virginia.edu 18311726Sar4jc@virginia.edu if (fault == NoFault) { 18411726Sar4jc@virginia.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 18511726Sar4jc@virginia.edu } 18611726Sar4jc@virginia.edu 18711726Sar4jc@virginia.edu if (fault == NoFault) { 18811726Sar4jc@virginia.edu %(code)s; 18911726Sar4jc@virginia.edu } 19011726Sar4jc@virginia.edu 19111726Sar4jc@virginia.edu if (fault == NoFault) { 19211726Sar4jc@virginia.edu %(op_wb)s; 19311726Sar4jc@virginia.edu } 19411726Sar4jc@virginia.edu 19511726Sar4jc@virginia.edu return fault; 19611726Sar4jc@virginia.edu } 19711726Sar4jc@virginia.edu}}; 19811726Sar4jc@virginia.edu 19911726Sar4jc@virginia.edudef template AtomicMemOpStoreExecute {{ 20011726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sStore::execute(CPU_EXEC_CONTEXT *xc, 20111726Sar4jc@virginia.edu Trace::InstRecord *traceData) const 20211726Sar4jc@virginia.edu { 20311726Sar4jc@virginia.edu Addr EA; 20411726Sar4jc@virginia.edu Fault fault = NoFault; 20511726Sar4jc@virginia.edu 20611726Sar4jc@virginia.edu %(op_decl)s; 20711726Sar4jc@virginia.edu %(op_rd)s; 20811726Sar4jc@virginia.edu %(ea_code)s; 20911726Sar4jc@virginia.edu 21011726Sar4jc@virginia.edu if (fault == NoFault) { 21111726Sar4jc@virginia.edu %(code)s; 21211726Sar4jc@virginia.edu } 21311726Sar4jc@virginia.edu 21411726Sar4jc@virginia.edu if (fault == NoFault) { 21511726Sar4jc@virginia.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 21611726Sar4jc@virginia.edu nullptr); 21711726Sar4jc@virginia.edu } 21811726Sar4jc@virginia.edu 21911726Sar4jc@virginia.edu if (fault == NoFault) { 22011726Sar4jc@virginia.edu %(op_wb)s; 22111726Sar4jc@virginia.edu } 22211726Sar4jc@virginia.edu 22311726Sar4jc@virginia.edu return fault; 22411726Sar4jc@virginia.edu } 22511726Sar4jc@virginia.edu}}; 22611726Sar4jc@virginia.edu 22711726Sar4jc@virginia.edudef template AtomicMemOpLoadEACompExecute {{ 22811726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sLoad::eaComp(CPU_EXEC_CONTEXT *xc, 22911726Sar4jc@virginia.edu Trace::InstRecord *traceData) const 23011726Sar4jc@virginia.edu { 23111726Sar4jc@virginia.edu Addr EA; 23211726Sar4jc@virginia.edu Fault fault = NoFault; 23311726Sar4jc@virginia.edu 23411726Sar4jc@virginia.edu %(op_decl)s; 23511726Sar4jc@virginia.edu %(op_rd)s; 23611726Sar4jc@virginia.edu %(ea_code)s; 23711726Sar4jc@virginia.edu 23811726Sar4jc@virginia.edu if (fault == NoFault) { 23911726Sar4jc@virginia.edu %(op_wb)s; 24011726Sar4jc@virginia.edu xc->setEA(EA); 24111726Sar4jc@virginia.edu } 24211726Sar4jc@virginia.edu 24311726Sar4jc@virginia.edu return fault; 24411726Sar4jc@virginia.edu } 24511726Sar4jc@virginia.edu}}; 24611726Sar4jc@virginia.edu 24711726Sar4jc@virginia.edudef template AtomicMemOpStoreEACompExecute {{ 24811726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sStore::eaComp(CPU_EXEC_CONTEXT *xc, 24911726Sar4jc@virginia.edu Trace::InstRecord *traceData) const 25011726Sar4jc@virginia.edu { 25111726Sar4jc@virginia.edu Addr EA; 25211726Sar4jc@virginia.edu Fault fault = NoFault; 25311726Sar4jc@virginia.edu 25411726Sar4jc@virginia.edu %(op_decl)s; 25511726Sar4jc@virginia.edu %(op_rd)s; 25611726Sar4jc@virginia.edu %(ea_code)s; 25711726Sar4jc@virginia.edu 25811726Sar4jc@virginia.edu if (fault == NoFault) { 25911726Sar4jc@virginia.edu %(op_wb)s; 26011726Sar4jc@virginia.edu xc->setEA(EA); 26111726Sar4jc@virginia.edu } 26211726Sar4jc@virginia.edu 26311726Sar4jc@virginia.edu return fault; 26411726Sar4jc@virginia.edu } 26511726Sar4jc@virginia.edu}}; 26611726Sar4jc@virginia.edu 26711726Sar4jc@virginia.edudef template AtomicMemOpLoadInitiateAcc {{ 26811726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sLoad::initiateAcc(CPU_EXEC_CONTEXT *xc, 26911726Sar4jc@virginia.edu Trace::InstRecord *traceData) const 27011726Sar4jc@virginia.edu { 27111726Sar4jc@virginia.edu Addr EA; 27211726Sar4jc@virginia.edu Fault fault = NoFault; 27311726Sar4jc@virginia.edu 27411726Sar4jc@virginia.edu %(op_src_decl)s; 27511726Sar4jc@virginia.edu %(op_rd)s; 27611726Sar4jc@virginia.edu %(ea_code)s; 27711726Sar4jc@virginia.edu 27811726Sar4jc@virginia.edu if (fault == NoFault) { 27911726Sar4jc@virginia.edu fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); 28011726Sar4jc@virginia.edu } 28111726Sar4jc@virginia.edu 28211726Sar4jc@virginia.edu return fault; 28311726Sar4jc@virginia.edu } 28411726Sar4jc@virginia.edu}}; 28511726Sar4jc@virginia.edu 28611726Sar4jc@virginia.edudef template AtomicMemOpStoreInitiateAcc {{ 28711726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sStore::initiateAcc( 28811726Sar4jc@virginia.edu CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 28911726Sar4jc@virginia.edu { 29011726Sar4jc@virginia.edu Addr EA; 29111726Sar4jc@virginia.edu Fault fault = NoFault; 29211726Sar4jc@virginia.edu 29311726Sar4jc@virginia.edu %(op_decl)s; 29411726Sar4jc@virginia.edu %(op_rd)s; 29511726Sar4jc@virginia.edu %(ea_code)s; 29611726Sar4jc@virginia.edu 29711726Sar4jc@virginia.edu if (fault == NoFault) { 29811726Sar4jc@virginia.edu %(code)s; 29911726Sar4jc@virginia.edu } 30011726Sar4jc@virginia.edu 30111726Sar4jc@virginia.edu if (fault == NoFault) { 30211726Sar4jc@virginia.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 30311726Sar4jc@virginia.edu nullptr); 30411726Sar4jc@virginia.edu } 30511726Sar4jc@virginia.edu 30611726Sar4jc@virginia.edu if (fault == NoFault) { 30711726Sar4jc@virginia.edu %(op_wb)s; 30811726Sar4jc@virginia.edu } 30911726Sar4jc@virginia.edu 31011726Sar4jc@virginia.edu return fault; 31111726Sar4jc@virginia.edu } 31211726Sar4jc@virginia.edu}}; 31311726Sar4jc@virginia.edu 31411726Sar4jc@virginia.edudef template AtomicMemOpLoadCompleteAcc {{ 31511726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sLoad::completeAcc(PacketPtr pkt, 31611726Sar4jc@virginia.edu CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 31711726Sar4jc@virginia.edu { 31811726Sar4jc@virginia.edu Fault fault = NoFault; 31911726Sar4jc@virginia.edu 32011726Sar4jc@virginia.edu %(op_decl)s; 32111726Sar4jc@virginia.edu %(op_rd)s; 32211726Sar4jc@virginia.edu 32311726Sar4jc@virginia.edu getMem(pkt, Mem, traceData); 32411726Sar4jc@virginia.edu 32511726Sar4jc@virginia.edu if (fault == NoFault) { 32611726Sar4jc@virginia.edu %(code)s; 32711726Sar4jc@virginia.edu } 32811726Sar4jc@virginia.edu 32911726Sar4jc@virginia.edu if (fault == NoFault) { 33011726Sar4jc@virginia.edu %(op_wb)s; 33111726Sar4jc@virginia.edu } 33211726Sar4jc@virginia.edu 33311726Sar4jc@virginia.edu return fault; 33411726Sar4jc@virginia.edu } 33511726Sar4jc@virginia.edu}}; 33611726Sar4jc@virginia.edu 33711726Sar4jc@virginia.edudef template AtomicMemOpStoreCompleteAcc {{ 33811726Sar4jc@virginia.edu Fault %(class_name)s::%(class_name)sStore::completeAcc(PacketPtr pkt, 33911726Sar4jc@virginia.edu CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 34011726Sar4jc@virginia.edu { 34111726Sar4jc@virginia.edu return NoFault; 34211726Sar4jc@virginia.edu } 34311726Sar4jc@virginia.edu}}; 34411726Sar4jc@virginia.edu 34511726Sar4jc@virginia.edudef format AtomicMemOp(load_code, store_code, ea_code, load_flags=[], 34611726Sar4jc@virginia.edu store_flags=[], inst_flags=[]) {{ 34711726Sar4jc@virginia.edu macro_iop = InstObjParams(name, Name, 'AtomicMemOp', ea_code, inst_flags) 34811726Sar4jc@virginia.edu header_output = AtomicMemOpDeclare.subst(macro_iop) 34911726Sar4jc@virginia.edu decoder_output = AtomicMemOpMacroConstructor.subst(macro_iop) 35011726Sar4jc@virginia.edu decode_block = AtomicMemOpMacroDecode.subst(macro_iop) 35111726Sar4jc@virginia.edu exec_output = '' 35211726Sar4jc@virginia.edu 35311726Sar4jc@virginia.edu load_inst_flags = makeList(inst_flags) + ["IsMemRef", "IsLoad"] 35411726Sar4jc@virginia.edu load_iop = InstObjParams(name, Name, 'AtomicMemOpMicro', 35511726Sar4jc@virginia.edu {'ea_code': ea_code, 'code': load_code}, load_inst_flags) 35611726Sar4jc@virginia.edu decoder_output += AtomicMemOpLoadConstructor.subst(load_iop) 35711726Sar4jc@virginia.edu exec_output += AtomicMemOpLoadExecute.subst(load_iop) \ 35811726Sar4jc@virginia.edu + AtomicMemOpLoadEACompExecute.subst(load_iop) \ 35911726Sar4jc@virginia.edu + AtomicMemOpLoadInitiateAcc.subst(load_iop) \ 36011726Sar4jc@virginia.edu + AtomicMemOpLoadCompleteAcc.subst(load_iop) 36111726Sar4jc@virginia.edu 36211726Sar4jc@virginia.edu store_inst_flags = makeList(inst_flags) + ["IsMemRef", "IsStore"] 36311726Sar4jc@virginia.edu store_iop = InstObjParams(name, Name, 'AtomicMemOpMicro', 36411726Sar4jc@virginia.edu {'ea_code': ea_code, 'code': store_code}, store_inst_flags) 36511726Sar4jc@virginia.edu decoder_output += AtomicMemOpStoreConstructor.subst(store_iop) 36611726Sar4jc@virginia.edu exec_output += AtomicMemOpStoreExecute.subst(store_iop) \ 36711726Sar4jc@virginia.edu + AtomicMemOpStoreEACompExecute.subst(store_iop) \ 36811726Sar4jc@virginia.edu + AtomicMemOpStoreInitiateAcc.subst(store_iop) \ 36911726Sar4jc@virginia.edu + AtomicMemOpStoreCompleteAcc.subst(store_iop) 37011726Sar4jc@virginia.edu}}; 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