interrupts.hh revision 13628 
1/*
2 * Copyright (c) 2011 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_RISCV_INTERRUPT_HH__
32#define __ARCH_RISCV_INTERRUPT_HH__
33
34#include <bitset>
35#include <memory>
36
37#include "arch/riscv/faults.hh"
38#include "arch/riscv/registers.hh"
39#include "base/logging.hh"
40#include "cpu/thread_context.hh"
41#include "debug/Interrupt.hh"
42#include "params/RiscvInterrupts.hh"
43#include "sim/sim_object.hh"
44
45class BaseCPU;
46class ThreadContext;
47
48namespace RiscvISA {
49
50/*
51 * This is based on version 1.10 of the RISC-V privileged ISA reference,
52 * chapter 3.1.14.
53 */
54class Interrupts : public SimObject
55{
56  private:
57    BaseCPU * cpu;
58    std::bitset<NumInterruptTypes> ip;
59    std::bitset<NumInterruptTypes> ie;
60
61  public:
62    typedef RiscvInterruptsParams Params;
63
64    const Params *
65    params() const
66    {
67        return dynamic_cast<const Params *>(_params);
68    }
69
70    Interrupts(Params * p) : SimObject(p), cpu(nullptr), ip(0), ie(0) {}
71
72    void setCPU(BaseCPU * _cpu) { cpu = _cpu; }
73
74    std::bitset<NumInterruptTypes>
75    globalMask(ThreadContext *tc) const
76    {
77        INTERRUPT mask;
78        STATUS status = tc->readMiscReg(MISCREG_STATUS);
79        if (status.mie)
80            mask.mei = mask.mti = mask.msi = 1;
81        if (status.sie)
82            mask.sei = mask.sti = mask.ssi = 1;
83        if (status.uie)
84            mask.uei = mask.uti = mask.usi = 1;
85        return std::bitset<NumInterruptTypes>(mask);
86    }
87
88    bool checkInterrupt(int num) const { return ip[num] && ie[num]; }
89    bool checkInterrupts(ThreadContext *tc) const
90    {
91        return (ip & ie & globalMask(tc)).any();
92    }
93
94    Fault
95    getInterrupt(ThreadContext *tc) const
96    {
97        assert(checkInterrupts(tc));
98        std::bitset<NumInterruptTypes> mask = globalMask(tc);
99        for (int c = 0; c < NumInterruptTypes; c++)
100            if (checkInterrupt(c) && mask[c])
101                return std::make_shared<InterruptFault>(c);
102        return NoFault;
103    }
104
105    void updateIntrInfo(ThreadContext *tc) {}
106
107    void
108    post(int int_num, int index)
109    {
110        DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
111        ip[int_num] = true;
112    }
113
114    void
115    clear(int int_num, int index)
116    {
117        DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
118        ip[int_num] = false;
119    }
120
121    void
122    clearAll()
123    {
124        DPRINTF(Interrupt, "All interrupts cleared\n");
125        ip = 0;
126    }
127
128    uint64_t readIP() const { return (uint64_t)ip.to_ulong(); }
129    uint64_t readIE() const { return (uint64_t)ie.to_ulong(); }
130    void setIP(const uint64_t& val) { ip = val; }
131    void setIE(const uint64_t& val) { ie = val; }
132
133    void
134    serialize(CheckpointOut &cp) const
135    {
136        SERIALIZE_SCALAR(ip.to_ulong());
137        SERIALIZE_SCALAR(ie.to_ulong());
138    }
139
140    void
141    unserialize(CheckpointIn &cp)
142    {
143        long reg;
144        UNSERIALIZE_SCALAR(reg);
145        ip = reg;
146        UNSERIALIZE_SCALAR(reg);
147        ie = reg;
148    }
149};
150
151} // namespace RiscvISA
152
153#endif // __ARCH_RISCV_INTERRUPT_HH__
154