interrupts.hh revision 11723 
1/*
2 * Copyright (c) 2011 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_RISCV_INTERRUPT_HH__
32#define __ARCH_RISCV_INTERRUPT_HH__
33
34#include "base/misc.hh"
35#include "params/RiscvInterrupts.hh"
36#include "sim/sim_object.hh"
37
38class ThreadContext;
39
40namespace RiscvISA {
41
42class Interrupts : public SimObject
43{
44  private:
45    BaseCPU * cpu;
46
47  public:
48    typedef RiscvInterruptsParams Params;
49
50    const Params *
51    params() const
52    {
53        return dynamic_cast<const Params *>(_params);
54    }
55
56    Interrupts(Params * p) : SimObject(p), cpu(nullptr)
57    {}
58
59    void
60    setCPU(BaseCPU * _cpu)
61    {
62        cpu = _cpu;
63    }
64
65    void
66    post(int int_num, int index)
67    {
68        panic("Interrupts::post not implemented.\n");
69    }
70
71    void
72    clear(int int_num, int index)
73    {
74        panic("Interrupts::clear not implemented.\n");
75    }
76
77    void
78    clearAll()
79    {
80        panic("Interrupts::clearAll not implemented.\n");
81    }
82
83    bool
84    checkInterrupts(ThreadContext *tc) const
85    {
86        panic("Interrupts::checkInterrupts not implemented.\n");
87    }
88
89    Fault
90    getInterrupt(ThreadContext *tc)
91    {
92        assert(checkInterrupts(tc));
93        panic("Interrupts::getInterrupt not implemented.\n");
94    }
95
96    void
97    updateIntrInfo(ThreadContext *tc)
98    {
99        panic("Interrupts::updateIntrInfo not implemented.\n");
100    }
101};
102
103} // namespace RiscvISA
104
105#endif // __ARCH_RISCV_INTERRUPT_HH__
106
107