static_inst.hh revision 12614
112SN/A/* 21762SN/A * Copyright (c) 2015 RISC-V Foundation 312SN/A * Copyright (c) 2016 The University of Virginia 412SN/A * All rights reserved. 512SN/A * 612SN/A * Redistribution and use in source and binary forms, with or without 712SN/A * modification, are permitted provided that the following conditions are 812SN/A * met: redistributions of source code must retain the above copyright 912SN/A * notice, this list of conditions and the following disclaimer; 1012SN/A * redistributions in binary form must reproduce the above copyright 1112SN/A * notice, this list of conditions and the following disclaimer in the 1212SN/A * documentation and/or other materials provided with the distribution; 1312SN/A * neither the name of the copyright holders nor the names of its 1412SN/A * contributors may be used to endorse or promote products derived from 1512SN/A * this software without specific prior written permission. 1612SN/A * 1712SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1812SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1912SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2012SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2112SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2312SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2412SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2512SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2612SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 2912SN/A * Authors: Maxwell Walter 3012SN/A * Alec Roelke 3112SN/A */ 3212SN/A 3356SN/A#ifndef __ARCH_RISCV_STATIC_INST_HH__ 3456SN/A#define __ARCH_RISCV_STATIC_INST_HH__ 357676Snate@binkert.org 3656SN/A#include <string> 3712SN/A 3812SN/A#include "arch/riscv/types.hh" 3912SN/A#include "cpu/exec_context.hh" 4012SN/A#include "cpu/static_inst.hh" 4112SN/A#include "mem/packet.hh" 4212SN/A 4312SN/Anamespace RiscvISA 44360SN/A{ 45360SN/A 46360SN/A/** 4712SN/A * Base class for all RISC-V static instructions. 4812SN/A */ 4912SN/Aclass RiscvStaticInst : public StaticInst 5012SN/A{ 5112SN/A protected: 5212SN/A using StaticInst::StaticInst; 5312SN/A 5412SN/A virtual std::string 55360SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 56360SN/A 57360SN/A public: 5812SN/A void advancePC(PCState &pc) const { pc.advance(); } 5912SN/A 6012SN/A size_t 6112SN/A asBytes(void *buf, size_t size) override 6212SN/A { 6312SN/A return simpleAsBytes(buf, size, machInst); 6412SN/A } 652420SN/A}; 6612SN/A 6712SN/A/** 6812SN/A * Base class for all RISC-V Macroops 692420SN/A */ 7012SN/Aclass RiscvMacroInst : public RiscvStaticInst 7112SN/A{ 7212SN/A protected: 732420SN/A std::vector<StaticInstPtr> microops; 7412SN/A 7512SN/A RiscvMacroInst(const char *mnem, ExtMachInst _machInst, 7612SN/A OpClass __opClass) : 7712SN/A RiscvStaticInst(mnem, _machInst, __opClass) 7812SN/A { 7912SN/A flags[IsMacroop] = true; 8012SN/A } 8112SN/A 823812Ssaidi@eecs.umich.edu ~RiscvMacroInst() { microops.clear(); } 8312SN/A 8412SN/A StaticInstPtr 8512SN/A fetchMicroop(MicroPC upc) const override 8612SN/A { 8712SN/A return microops[upc]; 8812SN/A } 893812Ssaidi@eecs.umich.edu 9012SN/A Fault 9112SN/A initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override 9212SN/A { 9312SN/A panic("Tried to execute a macroop directly!\n"); 94 } 95 96 Fault 97 completeAcc(PacketPtr pkt, ExecContext *xc, 98 Trace::InstRecord *traceData) const override 99 { 100 panic("Tried to execute a macroop directly!\n"); 101 } 102 103 Fault 104 execute(ExecContext *xc, Trace::InstRecord *traceData) const override 105 { 106 panic("Tried to execute a macroop directly!\n"); 107 } 108}; 109 110/** 111 * Base class for all RISC-V Microops 112 */ 113class RiscvMicroInst : public RiscvStaticInst 114{ 115 protected: 116 RiscvMicroInst(const char *mnem, ExtMachInst _machInst, 117 OpClass __opClass) : 118 RiscvStaticInst(mnem, _machInst, __opClass) 119 { 120 flags[IsMicroop] = true; 121 } 122 123 void advancePC(PCState &pcState) const; 124}; 125 126} 127 128#endif // __ARCH_RISCV_STATIC_INST_HH__ 129