standard.cc revision 12438:c7514a2a926d
1/* 2 * Copyright (c) 2015 RISC-V Foundation 3 * Copyright (c) 2017 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Alec Roelke 30 */ 31 32#include "arch/riscv/insts/standard.hh" 33 34#include <sstream> 35#include <string> 36 37#include "arch/riscv/insts/static_inst.hh" 38#include "arch/riscv/utility.hh" 39#include "cpu/static_inst.hh" 40 41using namespace std; 42 43namespace RiscvISA 44{ 45 46string 47RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 48{ 49 stringstream ss; 50 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << 51 registerName(_srcRegIdx[0]) << ", " << 52 registerName(_srcRegIdx[1]); 53 return ss.str(); 54} 55 56string 57CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 58{ 59 stringstream ss; 60 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "; 61 if (_numSrcRegs > 0) 62 ss << registerName(_srcRegIdx[0]) << ", "; 63 auto name = MiscRegNames.find(csr); 64 if (name != MiscRegNames.end()) 65 ss << name->second; 66 else 67 ss << "?? (" << hex << "0x" << csr << ")"; 68 return ss.str(); 69} 70 71}