amo.hh revision 12323:55d08b81ff39
14479Sbinkertn@umich.edu/* 24479Sbinkertn@umich.edu * Copyright (c) 2015 RISC-V Foundation 34479Sbinkertn@umich.edu * Copyright (c) 2017 The University of Virginia 44479Sbinkertn@umich.edu * All rights reserved. 54479Sbinkertn@umich.edu * 64479Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 74479Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 84479Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 94479Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 104479Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 114479Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 124479Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 134479Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 144479Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 154479Sbinkertn@umich.edu * this software without specific prior written permission. 164479Sbinkertn@umich.edu * 174479Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 184479Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 194479Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 204479Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 214479Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 224479Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 234479Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 244479Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 254479Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 264479Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 274479Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284479Sbinkertn@umich.edu * 294479Sbinkertn@umich.edu * Authors: Alec Roelke 304479Sbinkertn@umich.edu */ 314479Sbinkertn@umich.edu 324479Sbinkertn@umich.edu#ifndef __ARCH_RISCV_INSTS_AMO_HH__ 334479Sbinkertn@umich.edu#define __ARCH_RISCV_INSTS_AMO_HH__ 344479Sbinkertn@umich.edu 354479Sbinkertn@umich.edu#include <string> 364479Sbinkertn@umich.edu 374479Sbinkertn@umich.edu#include "arch/riscv/insts/mem.hh" 384479Sbinkertn@umich.edu#include "arch/riscv/insts/static_inst.hh" 394479Sbinkertn@umich.edu#include "cpu/static_inst.hh" 404479Sbinkertn@umich.edu 414479Sbinkertn@umich.edunamespace RiscvISA 424479Sbinkertn@umich.edu{ 434479Sbinkertn@umich.edu 444479Sbinkertn@umich.educlass LoadReserved : public MemInst 454479Sbinkertn@umich.edu{ 464479Sbinkertn@umich.edu protected: 474479Sbinkertn@umich.edu using MemInst::MemInst; 484479Sbinkertn@umich.edu 494479Sbinkertn@umich.edu std::string generateDisassembly( 504479Sbinkertn@umich.edu Addr pc, const SymbolTable *symtab) const override; 514479Sbinkertn@umich.edu}; 524479Sbinkertn@umich.edu 534479Sbinkertn@umich.educlass StoreCond : public MemInst 544479Sbinkertn@umich.edu{ 554479Sbinkertn@umich.edu protected: 564479Sbinkertn@umich.edu using MemInst::MemInst; 574479Sbinkertn@umich.edu 584479Sbinkertn@umich.edu std::string generateDisassembly( 594479Sbinkertn@umich.edu Addr pc, const SymbolTable *symtab) const override; 604479Sbinkertn@umich.edu}; 614479Sbinkertn@umich.edu 624479Sbinkertn@umich.educlass AtomicMemOp : public RiscvMacroInst 634479Sbinkertn@umich.edu{ 644479Sbinkertn@umich.edu protected: 654479Sbinkertn@umich.edu using RiscvMacroInst::RiscvMacroInst; 664479Sbinkertn@umich.edu 674479Sbinkertn@umich.edu std::string generateDisassembly( 684479Sbinkertn@umich.edu Addr pc, const SymbolTable *symtab) const override; 69}; 70 71class AtomicMemOpMicro : public RiscvMicroInst 72{ 73 protected: 74 Request::Flags memAccessFlags; 75 using RiscvMicroInst::RiscvMicroInst; 76 77 std::string generateDisassembly( 78 Addr pc, const SymbolTable *symtab) const override; 79}; 80 81} 82 83#endif // __ARCH_RISCV_INSTS_AMO_HH__