amo.cc revision 13653
112323Sar4jc@virginia.edu/* 212323Sar4jc@virginia.edu * Copyright (c) 2015 RISC-V Foundation 312323Sar4jc@virginia.edu * Copyright (c) 2017 The University of Virginia 412323Sar4jc@virginia.edu * All rights reserved. 512323Sar4jc@virginia.edu * 612323Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 712323Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 812323Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 912323Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 1012323Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1112323Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1212323Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1312323Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1412323Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1512323Sar4jc@virginia.edu * this software without specific prior written permission. 1612323Sar4jc@virginia.edu * 1712323Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1812323Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1912323Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2012323Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2112323Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2212323Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2312323Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2412323Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2512323Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2612323Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2712323Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2812323Sar4jc@virginia.edu * 2912323Sar4jc@virginia.edu * Authors: Alec Roelke 3012323Sar4jc@virginia.edu */ 3112323Sar4jc@virginia.edu 3212323Sar4jc@virginia.edu#include "arch/riscv/insts/amo.hh" 3312323Sar4jc@virginia.edu 3412323Sar4jc@virginia.edu#include <sstream> 3512323Sar4jc@virginia.edu#include <string> 3612323Sar4jc@virginia.edu 3712323Sar4jc@virginia.edu#include "arch/riscv/utility.hh" 3812323Sar4jc@virginia.edu#include "cpu/exec_context.hh" 3912323Sar4jc@virginia.edu#include "cpu/static_inst.hh" 4012323Sar4jc@virginia.edu 4112323Sar4jc@virginia.eduusing namespace std; 4212323Sar4jc@virginia.edu 4312323Sar4jc@virginia.edunamespace RiscvISA 4412323Sar4jc@virginia.edu{ 4512323Sar4jc@virginia.edu 4613653Sqtt2@cornell.edu// memfence micro instruction 4713653Sqtt2@cornell.edustring MemFenceMicro::generateDisassembly(Addr pc, 4813653Sqtt2@cornell.edu const SymbolTable *symtab) const 4913653Sqtt2@cornell.edu{ 5013653Sqtt2@cornell.edu stringstream ss; 5113653Sqtt2@cornell.edu ss << csprintf("0x%08x", machInst) << ' ' << mnemonic; 5213653Sqtt2@cornell.edu return ss.str(); 5313653Sqtt2@cornell.edu} 5413653Sqtt2@cornell.edu 5513653Sqtt2@cornell.eduFault MemFenceMicro::execute(ExecContext *xc, 5613653Sqtt2@cornell.edu Trace::InstRecord *traceData) const 5713653Sqtt2@cornell.edu{ 5813653Sqtt2@cornell.edu return NoFault; 5913653Sqtt2@cornell.edu} 6013653Sqtt2@cornell.edu 6113653Sqtt2@cornell.edu// load-reserved 6212323Sar4jc@virginia.edustring LoadReserved::generateDisassembly(Addr pc, 6312323Sar4jc@virginia.edu const SymbolTable *symtab) const 6412323Sar4jc@virginia.edu{ 6512323Sar4jc@virginia.edu stringstream ss; 6612323Sar4jc@virginia.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", (" 6712323Sar4jc@virginia.edu << registerName(_srcRegIdx[0]) << ')'; 6812323Sar4jc@virginia.edu return ss.str(); 6912323Sar4jc@virginia.edu} 7012323Sar4jc@virginia.edu 7113653Sqtt2@cornell.edustring LoadReservedMicro::generateDisassembly(Addr pc, 7213653Sqtt2@cornell.edu const SymbolTable *symtab) const 7313653Sqtt2@cornell.edu{ 7413653Sqtt2@cornell.edu stringstream ss; 7513653Sqtt2@cornell.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", (" 7613653Sqtt2@cornell.edu << registerName(_srcRegIdx[0]) << ')'; 7713653Sqtt2@cornell.edu return ss.str(); 7813653Sqtt2@cornell.edu} 7913653Sqtt2@cornell.edu 8013653Sqtt2@cornell.edu// store-conditional 8112323Sar4jc@virginia.edustring StoreCond::generateDisassembly(Addr pc, 8212323Sar4jc@virginia.edu const SymbolTable *symtab) const 8312323Sar4jc@virginia.edu{ 8412323Sar4jc@virginia.edu stringstream ss; 8512323Sar4jc@virginia.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 8612323Sar4jc@virginia.edu << registerName(_srcRegIdx[1]) << ", (" 8712323Sar4jc@virginia.edu << registerName(_srcRegIdx[0]) << ')'; 8812323Sar4jc@virginia.edu return ss.str(); 8912323Sar4jc@virginia.edu} 9012323Sar4jc@virginia.edu 9113653Sqtt2@cornell.edustring StoreCondMicro::generateDisassembly(Addr pc, 9213653Sqtt2@cornell.edu const SymbolTable *symtab) const 9313653Sqtt2@cornell.edu{ 9413653Sqtt2@cornell.edu stringstream ss; 9513653Sqtt2@cornell.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 9613653Sqtt2@cornell.edu << registerName(_srcRegIdx[1]) << ", (" 9713653Sqtt2@cornell.edu << registerName(_srcRegIdx[0]) << ')'; 9813653Sqtt2@cornell.edu return ss.str(); 9913653Sqtt2@cornell.edu} 10013653Sqtt2@cornell.edu 10113653Sqtt2@cornell.edu// AMOs 10212323Sar4jc@virginia.edustring AtomicMemOp::generateDisassembly(Addr pc, 10312323Sar4jc@virginia.edu const SymbolTable *symtab) const 10412323Sar4jc@virginia.edu{ 10512323Sar4jc@virginia.edu stringstream ss; 10612323Sar4jc@virginia.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 10712323Sar4jc@virginia.edu << registerName(_srcRegIdx[1]) << ", (" 10812323Sar4jc@virginia.edu << registerName(_srcRegIdx[0]) << ')'; 10912323Sar4jc@virginia.edu return ss.str(); 11012323Sar4jc@virginia.edu} 11112323Sar4jc@virginia.edu 11212323Sar4jc@virginia.edustring AtomicMemOpMicro::generateDisassembly(Addr pc, 11312323Sar4jc@virginia.edu const SymbolTable *symtab) const 11412323Sar4jc@virginia.edu{ 11512323Sar4jc@virginia.edu stringstream ss; 11613653Sqtt2@cornell.edu ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 11713653Sqtt2@cornell.edu << registerName(_srcRegIdx[1]) << ", (" 11813653Sqtt2@cornell.edu << registerName(_srcRegIdx[0]) << ')'; 11912323Sar4jc@virginia.edu return ss.str(); 12012323Sar4jc@virginia.edu} 12112323Sar4jc@virginia.edu 12213653Sqtt2@cornell.edu} 123