xref: /gem5/src/arch/riscv/SConscript

# -*- mode:python -*-

# Copyright (c) 2013 ARM Limited
# Copyright (c) 2014 Sven Karlsson
# All rights reserved
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2016 The University of Virginia
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#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
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# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
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# this software without specific prior written permission.
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# Authors: Andreas Hansson
#          Sven Karlsson
#          Alec Roelke

Import('*')

if env['TARGET_ISA'] == 'riscv':
    Source('decoder.cc')
    Source('faults.cc')
    Source('isa.cc')
    Source('interrupts.cc')
    Source('locked_mem.cc')
    Source('process.cc')
    Source('pagetable.cc')
    Source('remote_gdb.cc')
    Source('stacktrace.cc')
    Source('tlb.cc')
    Source('system.cc')

    Source('linux/process.cc')
    Source('linux/linux.cc')

    SimObject('RiscvInterrupts.py')
    SimObject('RiscvISA.py')
    SimObject('RiscvTLB.py')
    SimObject('RiscvSystem.py')

    DebugFlag('RiscvMisc')
    DebugFlag('RiscvTLB')

    # Add in files generated by the ISA description.
    env.ISADesc('isa/main.isa')