xref: /gem5/src/arch/riscv/RiscvISA.py

# Copyright (c) 2012 ARM Limited
# Copyright (c) 2014 Sven Karlsson
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# Copyright (c) 2016 RISC-V Foundation
# Copyright (c) 2016 The University of Virginia
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# Authors: Andreas Sandberg
#          Sven Karlsson
#          Alec Roelke

from m5.SimObject import SimObject

class RiscvISA(SimObject):
    type = 'RiscvISA'
    cxx_class = 'RiscvISA::ISA'
    cxx_header = "arch/riscv/isa.hh"