utility.hh revision 7720:65d338a8dba4 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Korey Sewell
31 *          Stephen Hines
32 *          Timothy M. Jones
33 */
34
35#ifndef __ARCH_POWER_UTILITY_HH__
36#define __ARCH_POWER_UTILITY_HH__
37
38#include "base/types.hh"
39#include "cpu/static_inst.hh"
40#include "cpu/thread_context.hh"
41
42namespace PowerISA {
43
44inline PCState
45buildRetPC(const PCState &curPC, const PCState &callPC)
46{
47    PCState retPC = callPC;
48    retPC.advance();
49    return retPC;
50}
51
52/**
53 * Function to ensure ISA semantics about 0 registers.
54 * @param tc The thread context.
55 */
56template <class TC>
57void zeroRegisters(TC *tc);
58
59inline void
60startupCPU(ThreadContext *tc, int cpuId)
61{
62    tc->activate(0);
63}
64
65void
66copyRegs(ThreadContext *src, ThreadContext *dest);
67
68static inline void
69copyMiscRegs(ThreadContext *src, ThreadContext *dest)
70{
71}
72
73void skipFunction(ThreadContext *tc);
74
75inline void
76advancePC(PCState &pc, const StaticInstPtr inst)
77{
78    pc.advance();
79}
80
81} // PowerISA namespace
82
83#endif // __ARCH_POWER_UTILITY_HH__
84