tlb.hh revision 6691:cd68b6ecd68d 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Authors: Nathan Binkert
32 *          Steve Reinhardt
33 *          Stephen Hines
34 *          Timothy M. Jones
35 */
36
37#ifndef __ARCH_POWER_TLB_HH__
38#define __ARCH_POWER_TLB_HH__
39
40#include <map>
41
42#include "arch/power/isa_traits.hh"
43#include "arch/power/utility.hh"
44#include "arch/power/vtophys.hh"
45#include "arch/power/pagetable.hh"
46#include "base/statistics.hh"
47#include "mem/request.hh"
48#include "params/PowerTLB.hh"
49#include "sim/faults.hh"
50#include "sim/tlb.hh"
51
52class ThreadContext;
53
54namespace PowerISA {
55
56// This is copied from the ARM ISA and has not been checked against the
57// Power at all.
58struct TlbEntry
59{
60    Addr _pageStart;
61
62    TlbEntry()
63    {
64    }
65
66    TlbEntry(Addr asn, Addr vaddr, Addr paddr)
67        : _pageStart(paddr)
68    {
69    }
70
71    void
72    updateVaddr(Addr new_vaddr)
73    {
74        panic("unimplemented");
75    }
76
77    Addr
78    pageStart()
79    {
80        return _pageStart;
81    }
82
83    void
84    serialize(std::ostream &os)
85    {
86        SERIALIZE_SCALAR(_pageStart);
87    }
88
89    void
90    unserialize(Checkpoint *cp, const std::string &section)
91    {
92        UNSERIALIZE_SCALAR(_pageStart);
93    }
94};
95
96class TLB : public BaseTLB
97{
98  protected:
99    typedef std::multimap<Addr, int> PageTable;
100    PageTable lookupTable;      // Quick lookup into page table
101
102    PowerISA::PTE *table;       // the Page Table
103    int size;                   // TLB Size
104    int nlu;                    // not last used entry (for replacement)
105
106    void
107    nextnlu()
108    {
109        if (++nlu >= size) {
110            nlu = 0;
111        }
112    }
113
114    PowerISA::PTE *lookup(Addr vpn, uint8_t asn) const;
115
116    mutable Stats::Scalar read_hits;
117    mutable Stats::Scalar read_misses;
118    mutable Stats::Scalar read_acv;
119    mutable Stats::Scalar read_accesses;
120    mutable Stats::Scalar write_hits;
121    mutable Stats::Scalar write_misses;
122    mutable Stats::Scalar write_acv;
123    mutable Stats::Scalar write_accesses;
124    Stats::Formula hits;
125    Stats::Formula misses;
126    Stats::Formula invalids;
127    Stats::Formula accesses;
128
129  public:
130    typedef PowerTLBParams Params;
131    TLB(const Params *p);
132    virtual ~TLB();
133
134    int probeEntry(Addr vpn,uint8_t) const;
135    PowerISA::PTE *getEntry(unsigned) const;
136
137    int smallPages;
138
139    int
140    getsize() const
141    {
142        return size;
143    }
144
145    PowerISA::PTE &index(bool advance = true);
146    void insert(Addr vaddr, PowerISA::PTE &pte);
147    void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages);
148    void flushAll();
149
150    void
151    demapPage(Addr vaddr, uint64_t asn)
152    {
153        panic("demapPage unimplemented.\n");
154    }
155
156    // static helper functions... really
157    static bool validVirtualAddress(Addr vaddr);
158    static Fault checkCacheability(RequestPtr &req);
159    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
160    void translateTiming(RequestPtr req, ThreadContext *tc,
161                         Translation *translation, Mode mode);
162
163    // Checkpointing
164    void serialize(std::ostream &os);
165    void unserialize(Checkpoint *cp, const std::string &section);
166    void regStats();
167};
168
169} // PowerISA namespace
170
171#endif // __ARCH_POWER_TLB_HH__
172