tlb.hh revision 10474:799c8ee4ecba
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * Copyright (c) 2007-2008 The Florida State University 5 * Copyright (c) 2009 The University of Edinburgh 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are 10 * met: redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer; 12 * redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution; 15 * neither the name of the copyright holders nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Authors: Nathan Binkert 32 * Steve Reinhardt 33 * Stephen Hines 34 * Timothy M. Jones 35 */ 36 37#ifndef __ARCH_POWER_TLB_HH__ 38#define __ARCH_POWER_TLB_HH__ 39 40#include <map> 41 42#include "arch/power/isa_traits.hh" 43#include "arch/power/pagetable.hh" 44#include "arch/power/utility.hh" 45#include "arch/power/vtophys.hh" 46#include "base/statistics.hh" 47#include "mem/request.hh" 48#include "params/PowerTLB.hh" 49#include "sim/tlb.hh" 50 51class ThreadContext; 52 53namespace PowerISA { 54 55// This is copied from the ARM ISA and has not been checked against the 56// Power at all. 57struct TlbEntry 58{ 59 Addr _pageStart; 60 61 TlbEntry() 62 { 63 } 64 65 TlbEntry(Addr asn, Addr vaddr, Addr paddr) 66 : _pageStart(paddr) 67 { 68 } 69 70 void 71 updateVaddr(Addr new_vaddr) 72 { 73 panic("unimplemented"); 74 } 75 76 Addr 77 pageStart() 78 { 79 return _pageStart; 80 } 81 82 void 83 serialize(std::ostream &os) 84 { 85 SERIALIZE_SCALAR(_pageStart); 86 } 87 88 void 89 unserialize(Checkpoint *cp, const std::string §ion) 90 { 91 UNSERIALIZE_SCALAR(_pageStart); 92 } 93}; 94 95class TLB : public BaseTLB 96{ 97 protected: 98 typedef std::multimap<Addr, int> PageTable; 99 PageTable lookupTable; // Quick lookup into page table 100 101 PowerISA::PTE *table; // the Page Table 102 int size; // TLB Size 103 int nlu; // not last used entry (for replacement) 104 105 void 106 nextnlu() 107 { 108 if (++nlu >= size) { 109 nlu = 0; 110 } 111 } 112 113 PowerISA::PTE *lookup(Addr vpn, uint8_t asn) const; 114 115 mutable Stats::Scalar read_hits; 116 mutable Stats::Scalar read_misses; 117 mutable Stats::Scalar read_acv; 118 mutable Stats::Scalar read_accesses; 119 mutable Stats::Scalar write_hits; 120 mutable Stats::Scalar write_misses; 121 mutable Stats::Scalar write_acv; 122 mutable Stats::Scalar write_accesses; 123 Stats::Formula hits; 124 Stats::Formula misses; 125 Stats::Formula accesses; 126 127 public: 128 typedef PowerTLBParams Params; 129 TLB(const Params *p); 130 virtual ~TLB(); 131 132 void takeOverFrom(BaseTLB *otlb) {} 133 134 int probeEntry(Addr vpn,uint8_t) const; 135 PowerISA::PTE *getEntry(unsigned) const; 136 137 int smallPages; 138 139 int 140 getsize() const 141 { 142 return size; 143 } 144 145 PowerISA::PTE &index(bool advance = true); 146 void insert(Addr vaddr, PowerISA::PTE &pte); 147 void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages); 148 void flushAll(); 149 150 void 151 demapPage(Addr vaddr, uint64_t asn) 152 { 153 panic("demapPage unimplemented.\n"); 154 } 155 156 // static helper functions... really 157 static bool validVirtualAddress(Addr vaddr); 158 static Fault checkCacheability(RequestPtr &req); 159 Fault translateInst(RequestPtr req, ThreadContext *tc); 160 Fault translateData(RequestPtr req, ThreadContext *tc, bool write); 161 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 162 void translateTiming(RequestPtr req, ThreadContext *tc, 163 Translation *translation, Mode mode); 164 /** Stub function for CheckerCPU compilation support. Power ISA not 165 * supported by Checker at the moment 166 */ 167 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); 168 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 169 170 // Checkpointing 171 void serialize(std::ostream &os); 172 void unserialize(Checkpoint *cp, const std::string §ion); 173 void regStats(); 174}; 175 176} // namespace PowerISA 177 178#endif // __ARCH_POWER_TLB_HH__ 179