tlb.hh revision 10558
12207SN/A/* 25254Sksewell@umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 42207SN/A * Copyright (c) 2007-2008 The Florida State University 55254Sksewell@umich.edu * Copyright (c) 2009 The University of Edinburgh 65254Sksewell@umich.edu * All rights reserved. 75254Sksewell@umich.edu * 85254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 95254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 105254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 125254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 135254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 145254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 152207SN/A * neither the name of the copyright holders nor the names of its 165254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 175254Sksewell@umich.edu * this software without specific prior written permission. 185254Sksewell@umich.edu * 195254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 205254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 215254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 225254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 235254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 245254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 255254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 265254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 272665Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 285254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 295254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 305254Sksewell@umich.edu * 312207SN/A * Authors: Nathan Binkert 322207SN/A * Steve Reinhardt 332474SN/A * Stephen Hines 342207SN/A * Timothy M. Jones 358229Snate@binkert.org */ 362454SN/A 372454SN/A#ifndef __ARCH_POWER_TLB_HH__ 382680Sktlim@umich.edu#define __ARCH_POWER_TLB_HH__ 398232Snate@binkert.org 406650Sksewell@umich.edu#include <map> 416650Sksewell@umich.edu 426650Sksewell@umich.edu#include "arch/power/isa_traits.hh" 432474SN/A#include "arch/power/pagetable.hh" 442207SN/A#include "arch/power/utility.hh" 452447SN/A#include "arch/power/vtophys.hh" 462474SN/A#include "base/statistics.hh" 472447SN/A#include "mem/request.hh" 485154Sgblack@eecs.umich.edu#include "params/PowerTLB.hh" 495154Sgblack@eecs.umich.edu#include "sim/tlb.hh" 505154Sgblack@eecs.umich.edu 512474SN/Aclass ThreadContext; 522686Sksewell@umich.edu 532686Sksewell@umich.edunamespace PowerISA { 542935Sksewell@umich.edu 552474SN/A// This is copied from the ARM ISA and has not been checked against the 562474SN/A// Power at all. 572474SN/Astruct TlbEntry 582474SN/A{ 592686Sksewell@umich.edu Addr _pageStart; 602686Sksewell@umich.edu 6110318Sandreas.hansson@arm.com TlbEntry() 622686Sksewell@umich.edu { 636811SMatt DeVuyst } 6411386Ssteve.reinhardt@amd.com 652474SN/A TlbEntry(Addr asn, Addr vaddr, Addr paddr, 662474SN/A bool uncacheable, bool read_only) 672474SN/A : _pageStart(paddr) 687532Ssteve.reinhardt@amd.com { 692474SN/A if (uncacheable || read_only) 707532Ssteve.reinhardt@amd.com warn("Power TlbEntry does not support uncacheable" 716650Sksewell@umich.edu " or read-only mappings\n"); 7210318Sandreas.hansson@arm.com } 732474SN/A 745958Sgblack@eecs.umich.edu void 756811SMatt DeVuyst updateVaddr(Addr new_vaddr) 766650Sksewell@umich.edu { 776811SMatt DeVuyst panic("unimplemented"); 786650Sksewell@umich.edu } 796811SMatt DeVuyst 806811SMatt DeVuyst Addr 8111389Sbrandon.potter@amd.com pageStart() 8211389Sbrandon.potter@amd.com { 8311389Sbrandon.potter@amd.com return _pageStart; 846650Sksewell@umich.edu } 856650Sksewell@umich.edu 866650Sksewell@umich.edu void 876811SMatt DeVuyst serialize(std::ostream &os) 886811SMatt DeVuyst { 896811SMatt DeVuyst SERIALIZE_SCALAR(_pageStart); 906811SMatt DeVuyst } 916811SMatt DeVuyst 926811SMatt DeVuyst void 936811SMatt DeVuyst unserialize(Checkpoint *cp, const std::string §ion) 9410318Sandreas.hansson@arm.com { 956811SMatt DeVuyst UNSERIALIZE_SCALAR(_pageStart); 966811SMatt DeVuyst } 976811SMatt DeVuyst}; 986811SMatt DeVuyst 996811SMatt DeVuystclass TLB : public BaseTLB 1006811SMatt DeVuyst{ 1016811SMatt DeVuyst protected: 1026811SMatt DeVuyst typedef std::multimap<Addr, int> PageTable; 1036811SMatt DeVuyst PageTable lookupTable; // Quick lookup into page table 1046811SMatt DeVuyst 1056811SMatt DeVuyst PowerISA::PTE *table; // the Page Table 10611389Sbrandon.potter@amd.com int size; // TLB Size 10711389Sbrandon.potter@amd.com int nlu; // not last used entry (for replacement) 10811389Sbrandon.potter@amd.com 10911389Sbrandon.potter@amd.com void 1106811SMatt DeVuyst nextnlu() 1116811SMatt DeVuyst { 1126811SMatt DeVuyst if (++nlu >= size) { 1136811SMatt DeVuyst nlu = 0; 1146811SMatt DeVuyst } 1156811SMatt DeVuyst } 1166811SMatt DeVuyst 1176811SMatt DeVuyst PowerISA::PTE *lookup(Addr vpn, uint8_t asn) const; 1186811SMatt DeVuyst 1196811SMatt DeVuyst mutable Stats::Scalar read_hits; 1206650Sksewell@umich.edu mutable Stats::Scalar read_misses; 1216650Sksewell@umich.edu mutable Stats::Scalar read_acv; 1226811SMatt DeVuyst mutable Stats::Scalar read_accesses; 1236811SMatt DeVuyst mutable Stats::Scalar write_hits; 1246650Sksewell@umich.edu mutable Stats::Scalar write_misses; 1256650Sksewell@umich.edu mutable Stats::Scalar write_acv; 1266650Sksewell@umich.edu mutable Stats::Scalar write_accesses; 1276650Sksewell@umich.edu Stats::Formula hits; 1286650Sksewell@umich.edu Stats::Formula misses; 1296650Sksewell@umich.edu Stats::Formula accesses; 1306650Sksewell@umich.edu 1316650Sksewell@umich.edu public: 1326650Sksewell@umich.edu typedef PowerTLBParams Params; 1336650Sksewell@umich.edu TLB(const Params *p); 1346811SMatt DeVuyst virtual ~TLB(); 1356811SMatt DeVuyst 1366811SMatt DeVuyst void takeOverFrom(BaseTLB *otlb) {} 1376811SMatt DeVuyst 1386811SMatt DeVuyst int probeEntry(Addr vpn,uint8_t) const; 1396650Sksewell@umich.edu PowerISA::PTE *getEntry(unsigned) const; 1406650Sksewell@umich.edu 1416650Sksewell@umich.edu int smallPages; 1426650Sksewell@umich.edu 1436650Sksewell@umich.edu int 1446650Sksewell@umich.edu getsize() const 1456650Sksewell@umich.edu { 1468601Ssteve.reinhardt@amd.com return size; 1476650Sksewell@umich.edu } 1486650Sksewell@umich.edu 1496811SMatt DeVuyst PowerISA::PTE &index(bool advance = true); 1506811SMatt DeVuyst void insert(Addr vaddr, PowerISA::PTE &pte); 1516811SMatt DeVuyst void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages); 1526811SMatt DeVuyst void flushAll(); 1536811SMatt DeVuyst 1546650Sksewell@umich.edu void 1556650Sksewell@umich.edu demapPage(Addr vaddr, uint64_t asn) 1566811SMatt DeVuyst { 1576650Sksewell@umich.edu panic("demapPage unimplemented.\n"); 1586811SMatt DeVuyst } 1596650Sksewell@umich.edu 1608852Sandreas.hansson@arm.com // static helper functions... really 1616650Sksewell@umich.edu static bool validVirtualAddress(Addr vaddr); 1626650Sksewell@umich.edu static Fault checkCacheability(RequestPtr &req); 1636650Sksewell@umich.edu Fault translateInst(RequestPtr req, ThreadContext *tc); 1646650Sksewell@umich.edu Fault translateData(RequestPtr req, ThreadContext *tc, bool write); 1656650Sksewell@umich.edu Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 1666811SMatt DeVuyst void translateTiming(RequestPtr req, ThreadContext *tc, 1676811SMatt DeVuyst Translation *translation, Mode mode); 1688852Sandreas.hansson@arm.com /** Stub function for CheckerCPU compilation support. Power ISA not 1696811SMatt DeVuyst * supported by Checker at the moment 1708852Sandreas.hansson@arm.com */ 1716811SMatt DeVuyst Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); 1726811SMatt DeVuyst Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 1736811SMatt DeVuyst 1746811SMatt DeVuyst // Checkpointing 1756811SMatt DeVuyst void serialize(std::ostream &os); 1766811SMatt DeVuyst void unserialize(Checkpoint *cp, const std::string §ion); 1776811SMatt DeVuyst void regStats(); 1788852Sandreas.hansson@arm.com}; 1796811SMatt DeVuyst 1806811SMatt DeVuyst} // namespace PowerISA 1816650Sksewell@umich.edu 1826650Sksewell@umich.edu#endif // __ARCH_POWER_TLB_HH__ 1836650Sksewell@umich.edu