tlb.cc revision 9738:304a37519d11
112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 312855Sgabeblack@google.com * Copyright (c) 2007 MIPS Technologies, Inc. 412855Sgabeblack@google.com * Copyright (c) 2007-2008 The Florida State University 512855Sgabeblack@google.com * Copyright (c) 2009 The University of Edinburgh 612855Sgabeblack@google.com * All rights reserved. 712855Sgabeblack@google.com * 812855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 912855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 1012855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 1112855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 1212855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1312855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1412855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1512855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1612855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1712855Sgabeblack@google.com * this software without specific prior written permission. 1812855Sgabeblack@google.com * 1912855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2012855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2112855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2212855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2312855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2412855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2512855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2612855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2712855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2812855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2912855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3012855Sgabeblack@google.com * 3112855Sgabeblack@google.com * Authors: Nathan Binkert 3212855Sgabeblack@google.com * Steve Reinhardt 3312855Sgabeblack@google.com * Jaidev Patwardhan 3412855Sgabeblack@google.com * Stephen Hines 3512855Sgabeblack@google.com * Timothy M. Jones 3612855Sgabeblack@google.com */ 3712855Sgabeblack@google.com 3812855Sgabeblack@google.com#include <string> 3912855Sgabeblack@google.com#include <vector> 4012855Sgabeblack@google.com 4112855Sgabeblack@google.com#include "arch/power/faults.hh" 4212855Sgabeblack@google.com#include "arch/power/pagetable.hh" 4312855Sgabeblack@google.com#include "arch/power/tlb.hh" 4412855Sgabeblack@google.com#include "arch/power/utility.hh" 4512855Sgabeblack@google.com#include "base/inifile.hh" 4612855Sgabeblack@google.com#include "base/str.hh" 4712855Sgabeblack@google.com#include "base/trace.hh" 4812855Sgabeblack@google.com#include "cpu/thread_context.hh" 4912855Sgabeblack@google.com#include "debug/Power.hh" 5012855Sgabeblack@google.com#include "debug/TLB.hh" 5112855Sgabeblack@google.com#include "mem/page_table.hh" 5212855Sgabeblack@google.com#include "params/PowerTLB.hh" 5312855Sgabeblack@google.com#include "sim/full_system.hh" 5412855Sgabeblack@google.com#include "sim/process.hh" 5512855Sgabeblack@google.com 5612855Sgabeblack@google.comusing namespace std; 5712855Sgabeblack@google.comusing namespace PowerISA; 5812855Sgabeblack@google.com 5912855Sgabeblack@google.com/////////////////////////////////////////////////////////////////////// 6012855Sgabeblack@google.com// 6112855Sgabeblack@google.com// POWER TLB 6212855Sgabeblack@google.com// 6312855Sgabeblack@google.com 6412855Sgabeblack@google.com#define MODE2MASK(X) (1 << (X)) 6512855Sgabeblack@google.com 6612855Sgabeblack@google.comTLB::TLB(const Params *p) 6712855Sgabeblack@google.com : BaseTLB(p), size(p->size), nlu(0) 6812855Sgabeblack@google.com{ 6912855Sgabeblack@google.com table = new PowerISA::PTE[size]; 7012855Sgabeblack@google.com memset(table, 0, sizeof(PowerISA::PTE[size])); 7112855Sgabeblack@google.com smallPages = 0; 7212855Sgabeblack@google.com} 7312855Sgabeblack@google.com 7412855Sgabeblack@google.comTLB::~TLB() 7512855Sgabeblack@google.com{ 7612855Sgabeblack@google.com if (table) 7712855Sgabeblack@google.com delete [] table; 7812855Sgabeblack@google.com} 7912855Sgabeblack@google.com 8012855Sgabeblack@google.com// look up an entry in the TLB 8112855Sgabeblack@google.comPowerISA::PTE * 8212855Sgabeblack@google.comTLB::lookup(Addr vpn, uint8_t asn) const 8312855Sgabeblack@google.com{ 8412855Sgabeblack@google.com // assume not found... 8512855Sgabeblack@google.com PowerISA::PTE *retval = NULL; 8612855Sgabeblack@google.com PageTable::const_iterator i = lookupTable.find(vpn); 8712855Sgabeblack@google.com if (i != lookupTable.end()) { 8812855Sgabeblack@google.com while (i->first == vpn) { 8912855Sgabeblack@google.com int index = i->second; 9012855Sgabeblack@google.com PowerISA::PTE *pte = &table[index]; 9112855Sgabeblack@google.com Addr Mask = pte->Mask; 9212855Sgabeblack@google.com Addr InvMask = ~Mask; 9312855Sgabeblack@google.com Addr VPN = pte->VPN; 9412855Sgabeblack@google.com if (((vpn & InvMask) == (VPN & InvMask)) 9512855Sgabeblack@google.com && (pte->G || (asn == pte->asid))) { 9612855Sgabeblack@google.com 9712855Sgabeblack@google.com // We have a VPN + ASID Match 9812855Sgabeblack@google.com retval = pte; 9912855Sgabeblack@google.com break; 10012855Sgabeblack@google.com } 10112855Sgabeblack@google.com ++i; 102 } 103 } 104 105 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 106 retval ? "hit" : "miss", retval ? retval->PFN1 : 0); 107 return retval; 108} 109 110PowerISA::PTE* 111TLB::getEntry(unsigned Index) const 112{ 113 // Make sure that Index is valid 114 assert(Index<size); 115 return &table[Index]; 116} 117 118int 119TLB::probeEntry(Addr vpn,uint8_t asn) const 120{ 121 // assume not found... 122 int Ind = -1; 123 PageTable::const_iterator i = lookupTable.find(vpn); 124 if (i != lookupTable.end()) { 125 while (i->first == vpn) { 126 int index = i->second; 127 PowerISA::PTE *pte = &table[index]; 128 Addr Mask = pte->Mask; 129 Addr InvMask = ~Mask; 130 Addr VPN = pte->VPN; 131 if (((vpn & InvMask) == (VPN & InvMask)) 132 && (pte->G || (asn == pte->asid))) { 133 134 // We have a VPN + ASID Match 135 Ind = index; 136 break; 137 } 138 ++i; 139 } 140 } 141 142 DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind); 143 return Ind; 144} 145 146inline Fault 147TLB::checkCacheability(RequestPtr &req) 148{ 149 Addr VAddrUncacheable = 0xA0000000; 150 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 151 152 // mark request as uncacheable 153 req->setFlags(Request::UNCACHEABLE); 154 } 155 return NoFault; 156} 157 158void 159TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages) 160{ 161 smallPages=_smallPages; 162 if (Index > size){ 163 warn("Attempted to write at index (%d) beyond TLB size (%d)", 164 Index, size); 165 } else { 166 167 // Update TLB 168 if (table[Index].V0 == true || table[Index].V1 == true) { 169 170 // Previous entry is valid 171 PageTable::iterator i = lookupTable.find(table[Index].VPN); 172 lookupTable.erase(i); 173 } 174 table[Index]=pte; 175 176 // Update fast lookup table 177 lookupTable.insert(make_pair(table[Index].VPN, Index)); 178 } 179} 180 181// insert a new TLB entry 182void 183TLB::insert(Addr addr, PowerISA::PTE &pte) 184{ 185 fatal("TLB Insert not yet implemented\n"); 186} 187 188void 189TLB::flushAll() 190{ 191 DPRINTF(TLB, "flushAll\n"); 192 memset(table, 0, sizeof(PowerISA::PTE[size])); 193 lookupTable.clear(); 194 nlu = 0; 195} 196 197void 198TLB::serialize(ostream &os) 199{ 200 SERIALIZE_SCALAR(size); 201 SERIALIZE_SCALAR(nlu); 202 203 for (int i = 0; i < size; i++) { 204 nameOut(os, csprintf("%s.PTE%d", name(), i)); 205 table[i].serialize(os); 206 } 207} 208 209void 210TLB::unserialize(Checkpoint *cp, const string §ion) 211{ 212 UNSERIALIZE_SCALAR(size); 213 UNSERIALIZE_SCALAR(nlu); 214 215 for (int i = 0; i < size; i++) { 216 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 217 if (table[i].V0 || table[i].V1) { 218 lookupTable.insert(make_pair(table[i].VPN, i)); 219 } 220 } 221} 222 223void 224TLB::regStats() 225{ 226 read_hits 227 .name(name() + ".read_hits") 228 .desc("DTB read hits") 229 ; 230 231 read_misses 232 .name(name() + ".read_misses") 233 .desc("DTB read misses") 234 ; 235 236 237 read_accesses 238 .name(name() + ".read_accesses") 239 .desc("DTB read accesses") 240 ; 241 242 write_hits 243 .name(name() + ".write_hits") 244 .desc("DTB write hits") 245 ; 246 247 write_misses 248 .name(name() + ".write_misses") 249 .desc("DTB write misses") 250 ; 251 252 253 write_accesses 254 .name(name() + ".write_accesses") 255 .desc("DTB write accesses") 256 ; 257 258 hits 259 .name(name() + ".hits") 260 .desc("DTB hits") 261 ; 262 263 misses 264 .name(name() + ".misses") 265 .desc("DTB misses") 266 ; 267 268 accesses 269 .name(name() + ".accesses") 270 .desc("DTB accesses") 271 ; 272 273 hits = read_hits + write_hits; 274 misses = read_misses + write_misses; 275 accesses = read_accesses + write_accesses; 276} 277 278Fault 279TLB::translateInst(RequestPtr req, ThreadContext *tc) 280{ 281 // Instruction accesses must be word-aligned 282 if (req->getVaddr() & 0x3) { 283 DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), 284 req->getSize()); 285 return new AlignmentFault(); 286 } 287 288 Process * p = tc->getProcessPtr(); 289 290 Fault fault = p->pTable->translate(req); 291 if (fault != NoFault) 292 return fault; 293 294 return NoFault; 295} 296 297Fault 298TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 299{ 300 Process * p = tc->getProcessPtr(); 301 302 Fault fault = p->pTable->translate(req); 303 if (fault != NoFault) 304 return fault; 305 306 return NoFault; 307} 308 309Fault 310TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 311{ 312 if (FullSystem) 313 fatal("translate atomic not yet implemented in full system mode.\n"); 314 315 if (mode == Execute) 316 return translateInst(req, tc); 317 else 318 return translateData(req, tc, mode == Write); 319} 320 321void 322TLB::translateTiming(RequestPtr req, ThreadContext *tc, 323 Translation *translation, Mode mode) 324{ 325 assert(translation); 326 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 327} 328 329Fault 330TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 331{ 332 panic("Not implemented\n"); 333 return NoFault; 334} 335 336Fault 337TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 338{ 339 return NoFault; 340} 341 342PowerISA::PTE & 343TLB::index(bool advance) 344{ 345 PowerISA::PTE *pte = &table[nlu]; 346 347 if (advance) 348 nextnlu(); 349 350 return *pte; 351} 352 353PowerISA::TLB * 354PowerTLBParams::create() 355{ 356 return new PowerISA::TLB(this); 357} 358