tlb.cc revision 8772:a5a83fc04972 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Authors: Nathan Binkert
32 *          Steve Reinhardt
33 *          Jaidev Patwardhan
34 *          Stephen Hines
35 *          Timothy M. Jones
36 */
37
38#include <string>
39#include <vector>
40
41#include "arch/power/faults.hh"
42#include "arch/power/pagetable.hh"
43#include "arch/power/tlb.hh"
44#include "arch/power/utility.hh"
45#include "base/inifile.hh"
46#include "base/str.hh"
47#include "base/trace.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Power.hh"
50#include "debug/TLB.hh"
51#include "mem/page_table.hh"
52#include "params/PowerTLB.hh"
53#include "sim/full_system.hh"
54#include "sim/process.hh"
55
56using namespace std;
57using namespace PowerISA;
58
59///////////////////////////////////////////////////////////////////////
60//
61//  POWER TLB
62//
63
64#define MODE2MASK(X) (1 << (X))
65
66TLB::TLB(const Params *p)
67    : BaseTLB(p), size(p->size), nlu(0)
68{
69    table = new PowerISA::PTE[size];
70    memset(table, 0, sizeof(PowerISA::PTE[size]));
71    smallPages = 0;
72}
73
74TLB::~TLB()
75{
76    if (table)
77        delete [] table;
78}
79
80// look up an entry in the TLB
81PowerISA::PTE *
82TLB::lookup(Addr vpn, uint8_t asn) const
83{
84    // assume not found...
85    PowerISA::PTE *retval = NULL;
86    PageTable::const_iterator i = lookupTable.find(vpn);
87    if (i != lookupTable.end()) {
88        while (i->first == vpn) {
89            int index = i->second;
90            PowerISA::PTE *pte = &table[index];
91            Addr Mask = pte->Mask;
92            Addr InvMask = ~Mask;
93            Addr VPN  = pte->VPN;
94            if (((vpn & InvMask) == (VPN & InvMask))
95               && (pte->G  || (asn == pte->asid))) {
96
97                // We have a VPN + ASID Match
98                retval = pte;
99                break;
100            }
101            ++i;
102        }
103    }
104
105    DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
106            retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
107    return retval;
108}
109
110PowerISA::PTE*
111TLB::getEntry(unsigned Index) const
112{
113    // Make sure that Index is valid
114    assert(Index<size);
115    return &table[Index];
116}
117
118int
119TLB::probeEntry(Addr vpn,uint8_t asn) const
120{
121    // assume not found...
122    PowerISA::PTE *retval = NULL;
123    int Ind = -1;
124    PageTable::const_iterator i = lookupTable.find(vpn);
125    if (i != lookupTable.end()) {
126        while (i->first == vpn) {
127            int index = i->second;
128            PowerISA::PTE *pte = &table[index];
129            Addr Mask = pte->Mask;
130            Addr InvMask = ~Mask;
131            Addr VPN  = pte->VPN;
132            if (((vpn & InvMask) == (VPN & InvMask))
133                && (pte->G  || (asn == pte->asid))) {
134
135                // We have a VPN + ASID Match
136                retval = pte;
137                Ind = index;
138                break;
139            }
140            ++i;
141        }
142    }
143
144    DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
145    return Ind;
146}
147
148inline Fault
149TLB::checkCacheability(RequestPtr &req)
150{
151    Addr VAddrUncacheable = 0xA0000000;
152    if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
153
154        // mark request as uncacheable
155        req->setFlags(Request::UNCACHEABLE);
156    }
157    return NoFault;
158}
159
160void
161TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
162{
163    smallPages=_smallPages;
164    if (Index > size){
165        warn("Attempted to write at index (%d) beyond TLB size (%d)",
166             Index, size);
167    } else {
168
169        // Update TLB
170        if (table[Index].V0 == true || table[Index].V1 == true) {
171
172            // Previous entry is valid
173            PageTable::iterator i = lookupTable.find(table[Index].VPN);
174            lookupTable.erase(i);
175        }
176        table[Index]=pte;
177
178        // Update fast lookup table
179        lookupTable.insert(make_pair(table[Index].VPN, Index));
180    }
181}
182
183// insert a new TLB entry
184void
185TLB::insert(Addr addr, PowerISA::PTE &pte)
186{
187    fatal("TLB Insert not yet implemented\n");
188}
189
190void
191TLB::flushAll()
192{
193    DPRINTF(TLB, "flushAll\n");
194    memset(table, 0, sizeof(PowerISA::PTE[size]));
195    lookupTable.clear();
196    nlu = 0;
197}
198
199void
200TLB::serialize(ostream &os)
201{
202    SERIALIZE_SCALAR(size);
203    SERIALIZE_SCALAR(nlu);
204
205    for (int i = 0; i < size; i++) {
206        nameOut(os, csprintf("%s.PTE%d", name(), i));
207        table[i].serialize(os);
208    }
209}
210
211void
212TLB::unserialize(Checkpoint *cp, const string &section)
213{
214    UNSERIALIZE_SCALAR(size);
215    UNSERIALIZE_SCALAR(nlu);
216
217    for (int i = 0; i < size; i++) {
218        table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
219        if (table[i].V0 || table[i].V1) {
220            lookupTable.insert(make_pair(table[i].VPN, i));
221        }
222    }
223}
224
225void
226TLB::regStats()
227{
228    read_hits
229        .name(name() + ".read_hits")
230        .desc("DTB read hits")
231        ;
232
233    read_misses
234        .name(name() + ".read_misses")
235        .desc("DTB read misses")
236        ;
237
238
239    read_accesses
240        .name(name() + ".read_accesses")
241        .desc("DTB read accesses")
242        ;
243
244    write_hits
245        .name(name() + ".write_hits")
246        .desc("DTB write hits")
247        ;
248
249    write_misses
250        .name(name() + ".write_misses")
251        .desc("DTB write misses")
252        ;
253
254
255    write_accesses
256        .name(name() + ".write_accesses")
257        .desc("DTB write accesses")
258        ;
259
260    hits
261        .name(name() + ".hits")
262        .desc("DTB hits")
263        ;
264
265    misses
266        .name(name() + ".misses")
267        .desc("DTB misses")
268        ;
269
270    accesses
271        .name(name() + ".accesses")
272        .desc("DTB accesses")
273        ;
274
275    hits = read_hits + write_hits;
276    misses = read_misses + write_misses;
277    accesses = read_accesses + write_accesses;
278}
279
280Fault
281TLB::translateInst(RequestPtr req, ThreadContext *tc)
282{
283    // Instruction accesses must be word-aligned
284    if (req->getVaddr() & 0x3) {
285        DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
286                req->getSize());
287        return new AlignmentFault();
288    }
289
290     Process * p = tc->getProcessPtr();
291
292     Fault fault = p->pTable->translate(req);
293    if (fault != NoFault)
294        return fault;
295
296    return NoFault;
297}
298
299Fault
300TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
301{
302    Process * p = tc->getProcessPtr();
303
304    Fault fault = p->pTable->translate(req);
305    if (fault != NoFault)
306        return fault;
307
308    return NoFault;
309}
310
311Fault
312TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
313{
314    if (FullSystem) {
315        fatal("translate atomic not yet implemented in full system mode.\n");
316    } else {
317        if (mode == Execute)
318            return translateInst(req, tc);
319        else
320            return translateData(req, tc, mode == Write);
321    }
322}
323
324void
325TLB::translateTiming(RequestPtr req, ThreadContext *tc,
326                     Translation *translation, Mode mode)
327{
328    assert(translation);
329    translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
330}
331
332PowerISA::PTE &
333TLB::index(bool advance)
334{
335    PowerISA::PTE *pte = &table[nlu];
336
337    if (advance)
338        nextnlu();
339
340    return *pte;
341}
342
343PowerISA::TLB *
344PowerTLBParams::create()
345{
346    return new PowerISA::TLB(this);
347}
348