tlb.cc revision 7676:92274350b953
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * Copyright (c) 2007-2008 The Florida State University 5 * Copyright (c) 2009 The University of Edinburgh 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are 10 * met: redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer; 12 * redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution; 15 * neither the name of the copyright holders nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Authors: Nathan Binkert 32 * Steve Reinhardt 33 * Jaidev Patwardhan 34 * Stephen Hines 35 * Timothy M. Jones 36 */ 37 38#include <string> 39#include <vector> 40 41#include "arch/power/faults.hh" 42#include "arch/power/pagetable.hh" 43#include "arch/power/tlb.hh" 44#include "arch/power/utility.hh" 45#include "base/inifile.hh" 46#include "base/str.hh" 47#include "base/trace.hh" 48#include "cpu/thread_context.hh" 49#include "mem/page_table.hh" 50#include "params/PowerTLB.hh" 51#include "sim/process.hh" 52 53using namespace std; 54using namespace PowerISA; 55 56/////////////////////////////////////////////////////////////////////// 57// 58// POWER TLB 59// 60 61#define MODE2MASK(X) (1 << (X)) 62 63TLB::TLB(const Params *p) 64 : BaseTLB(p), size(p->size), nlu(0) 65{ 66 table = new PowerISA::PTE[size]; 67 memset(table, 0, sizeof(PowerISA::PTE[size])); 68 smallPages = 0; 69} 70 71TLB::~TLB() 72{ 73 if (table) 74 delete [] table; 75} 76 77// look up an entry in the TLB 78PowerISA::PTE * 79TLB::lookup(Addr vpn, uint8_t asn) const 80{ 81 // assume not found... 82 PowerISA::PTE *retval = NULL; 83 PageTable::const_iterator i = lookupTable.find(vpn); 84 if (i != lookupTable.end()) { 85 while (i->first == vpn) { 86 int index = i->second; 87 PowerISA::PTE *pte = &table[index]; 88 Addr Mask = pte->Mask; 89 Addr InvMask = ~Mask; 90 Addr VPN = pte->VPN; 91 if (((vpn & InvMask) == (VPN & InvMask)) 92 && (pte->G || (asn == pte->asid))) { 93 94 // We have a VPN + ASID Match 95 retval = pte; 96 break; 97 } 98 ++i; 99 } 100 } 101 102 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 103 retval ? "hit" : "miss", retval ? retval->PFN1 : 0); 104 return retval; 105} 106 107PowerISA::PTE* 108TLB::getEntry(unsigned Index) const 109{ 110 // Make sure that Index is valid 111 assert(Index<size); 112 return &table[Index]; 113} 114 115int 116TLB::probeEntry(Addr vpn,uint8_t asn) const 117{ 118 // assume not found... 119 PowerISA::PTE *retval = NULL; 120 int Ind = -1; 121 PageTable::const_iterator i = lookupTable.find(vpn); 122 if (i != lookupTable.end()) { 123 while (i->first == vpn) { 124 int index = i->second; 125 PowerISA::PTE *pte = &table[index]; 126 Addr Mask = pte->Mask; 127 Addr InvMask = ~Mask; 128 Addr VPN = pte->VPN; 129 if (((vpn & InvMask) == (VPN & InvMask)) 130 && (pte->G || (asn == pte->asid))) { 131 132 // We have a VPN + ASID Match 133 retval = pte; 134 Ind = index; 135 break; 136 } 137 ++i; 138 } 139 } 140 141 DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind); 142 return Ind; 143} 144 145inline Fault 146TLB::checkCacheability(RequestPtr &req) 147{ 148 Addr VAddrUncacheable = 0xA0000000; 149 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { 150 151 // mark request as uncacheable 152 req->setFlags(Request::UNCACHEABLE); 153 } 154 return NoFault; 155} 156 157void 158TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages) 159{ 160 smallPages=_smallPages; 161 if (Index > size){ 162 warn("Attempted to write at index (%d) beyond TLB size (%d)", 163 Index, size); 164 } else { 165 166 // Update TLB 167 if (table[Index].V0 == true || table[Index].V1 == true) { 168 169 // Previous entry is valid 170 PageTable::iterator i = lookupTable.find(table[Index].VPN); 171 lookupTable.erase(i); 172 } 173 table[Index]=pte; 174 175 // Update fast lookup table 176 lookupTable.insert(make_pair(table[Index].VPN, Index)); 177 } 178} 179 180// insert a new TLB entry 181void 182TLB::insert(Addr addr, PowerISA::PTE &pte) 183{ 184 fatal("TLB Insert not yet implemented\n"); 185} 186 187void 188TLB::flushAll() 189{ 190 DPRINTF(TLB, "flushAll\n"); 191 memset(table, 0, sizeof(PowerISA::PTE[size])); 192 lookupTable.clear(); 193 nlu = 0; 194} 195 196void 197TLB::serialize(ostream &os) 198{ 199 SERIALIZE_SCALAR(size); 200 SERIALIZE_SCALAR(nlu); 201 202 for (int i = 0; i < size; i++) { 203 nameOut(os, csprintf("%s.PTE%d", name(), i)); 204 table[i].serialize(os); 205 } 206} 207 208void 209TLB::unserialize(Checkpoint *cp, const string §ion) 210{ 211 UNSERIALIZE_SCALAR(size); 212 UNSERIALIZE_SCALAR(nlu); 213 214 for (int i = 0; i < size; i++) { 215 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 216 if (table[i].V0 || table[i].V1) { 217 lookupTable.insert(make_pair(table[i].VPN, i)); 218 } 219 } 220} 221 222void 223TLB::regStats() 224{ 225 read_hits 226 .name(name() + ".read_hits") 227 .desc("DTB read hits") 228 ; 229 230 read_misses 231 .name(name() + ".read_misses") 232 .desc("DTB read misses") 233 ; 234 235 236 read_accesses 237 .name(name() + ".read_accesses") 238 .desc("DTB read accesses") 239 ; 240 241 write_hits 242 .name(name() + ".write_hits") 243 .desc("DTB write hits") 244 ; 245 246 write_misses 247 .name(name() + ".write_misses") 248 .desc("DTB write misses") 249 ; 250 251 252 write_accesses 253 .name(name() + ".write_accesses") 254 .desc("DTB write accesses") 255 ; 256 257 hits 258 .name(name() + ".hits") 259 .desc("DTB hits") 260 ; 261 262 misses 263 .name(name() + ".misses") 264 .desc("DTB misses") 265 ; 266 267 accesses 268 .name(name() + ".accesses") 269 .desc("DTB accesses") 270 ; 271 272 hits = read_hits + write_hits; 273 misses = read_misses + write_misses; 274 accesses = read_accesses + write_accesses; 275} 276 277Fault 278TLB::translateInst(RequestPtr req, ThreadContext *tc) 279{ 280 // Instruction accesses must be word-aligned 281 if (req->getVaddr() & 0x3) { 282 DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), 283 req->getSize()); 284 return new AlignmentFault(); 285 } 286 287 Process * p = tc->getProcessPtr(); 288 289 Fault fault = p->pTable->translate(req); 290 if (fault != NoFault) 291 return fault; 292 293 return NoFault; 294} 295 296Fault 297TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 298{ 299 Process * p = tc->getProcessPtr(); 300 301 Fault fault = p->pTable->translate(req); 302 if (fault != NoFault) 303 return fault; 304 305 return NoFault; 306} 307 308Fault 309TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 310{ 311#if !FULL_SYSTEM 312 if (mode == Execute) 313 return translateInst(req, tc); 314 else 315 return translateData(req, tc, mode == Write); 316#else 317 fatal("translate atomic not yet implemented\n"); 318#endif 319} 320 321void 322TLB::translateTiming(RequestPtr req, ThreadContext *tc, 323 Translation *translation, Mode mode) 324{ 325 assert(translation); 326 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 327} 328 329PowerISA::PTE & 330TLB::index(bool advance) 331{ 332 PowerISA::PTE *pte = &table[nlu]; 333 334 if (advance) 335 nextnlu(); 336 337 return *pte; 338} 339 340PowerISA::TLB * 341PowerTLBParams::create() 342{ 343 return new PowerISA::TLB(this); 344} 345