tlb.cc revision 6972 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Authors: Nathan Binkert
32 *          Steve Reinhardt
33 *          Jaidev Patwardhan
34 *          Stephen Hines
35 *          Timothy M. Jones
36 */
37
38#include <string>
39#include <vector>
40
41#include "arch/power/faults.hh"
42#include "arch/power/pagetable.hh"
43#include "arch/power/tlb.hh"
44#include "arch/power/utility.hh"
45#include "base/inifile.hh"
46#include "base/str.hh"
47#include "base/trace.hh"
48#include "cpu/thread_context.hh"
49#include "mem/page_table.hh"
50#include "params/PowerTLB.hh"
51#include "sim/process.hh"
52
53
54using namespace std;
55using namespace PowerISA;
56
57///////////////////////////////////////////////////////////////////////
58//
59//  POWER TLB
60//
61
62#define MODE2MASK(X) (1 << (X))
63
64TLB::TLB(const Params *p)
65    : BaseTLB(p), size(p->size), nlu(0)
66{
67    table = new PowerISA::PTE[size];
68    memset(table, 0, sizeof(PowerISA::PTE[size]));
69    smallPages = 0;
70}
71
72TLB::~TLB()
73{
74    if (table)
75        delete [] table;
76}
77
78// look up an entry in the TLB
79PowerISA::PTE *
80TLB::lookup(Addr vpn, uint8_t asn) const
81{
82    // assume not found...
83    PowerISA::PTE *retval = NULL;
84    PageTable::const_iterator i = lookupTable.find(vpn);
85    if (i != lookupTable.end()) {
86        while (i->first == vpn) {
87            int index = i->second;
88            PowerISA::PTE *pte = &table[index];
89            Addr Mask = pte->Mask;
90            Addr InvMask = ~Mask;
91            Addr VPN  = pte->VPN;
92            if (((vpn & InvMask) == (VPN & InvMask))
93               && (pte->G  || (asn == pte->asid))) {
94
95                // We have a VPN + ASID Match
96                retval = pte;
97                break;
98            }
99            ++i;
100        }
101    }
102
103    DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
104            retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
105    return retval;
106}
107
108PowerISA::PTE*
109TLB::getEntry(unsigned Index) const
110{
111    // Make sure that Index is valid
112    assert(Index<size);
113    return &table[Index];
114}
115
116int
117TLB::probeEntry(Addr vpn,uint8_t asn) const
118{
119    // assume not found...
120    PowerISA::PTE *retval = NULL;
121    int Ind = -1;
122    PageTable::const_iterator i = lookupTable.find(vpn);
123    if (i != lookupTable.end()) {
124        while (i->first == vpn) {
125            int index = i->second;
126            PowerISA::PTE *pte = &table[index];
127            Addr Mask = pte->Mask;
128            Addr InvMask = ~Mask;
129            Addr VPN  = pte->VPN;
130            if (((vpn & InvMask) == (VPN & InvMask))
131                && (pte->G  || (asn == pte->asid))) {
132
133                // We have a VPN + ASID Match
134                retval = pte;
135                Ind = index;
136                break;
137            }
138            ++i;
139        }
140    }
141
142    DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
143    return Ind;
144}
145
146inline Fault
147TLB::checkCacheability(RequestPtr &req)
148{
149    Addr VAddrUncacheable = 0xA0000000;
150    if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
151
152        // mark request as uncacheable
153        req->setFlags(Request::UNCACHEABLE);
154    }
155    return NoFault;
156}
157
158void
159TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
160{
161    smallPages=_smallPages;
162    if (Index > size){
163        warn("Attempted to write at index (%d) beyond TLB size (%d)",
164             Index, size);
165    } else {
166
167        // Update TLB
168        if (table[Index].V0 == true || table[Index].V1 == true) {
169
170            // Previous entry is valid
171            PageTable::iterator i = lookupTable.find(table[Index].VPN);
172            lookupTable.erase(i);
173        }
174        table[Index]=pte;
175
176        // Update fast lookup table
177        lookupTable.insert(make_pair(table[Index].VPN, Index));
178    }
179}
180
181// insert a new TLB entry
182void
183TLB::insert(Addr addr, PowerISA::PTE &pte)
184{
185    fatal("TLB Insert not yet implemented\n");
186}
187
188void
189TLB::flushAll()
190{
191    DPRINTF(TLB, "flushAll\n");
192    memset(table, 0, sizeof(PowerISA::PTE[size]));
193    lookupTable.clear();
194    nlu = 0;
195}
196
197void
198TLB::serialize(ostream &os)
199{
200    SERIALIZE_SCALAR(size);
201    SERIALIZE_SCALAR(nlu);
202
203    for (int i = 0; i < size; i++) {
204        nameOut(os, csprintf("%s.PTE%d", name(), i));
205        table[i].serialize(os);
206    }
207}
208
209void
210TLB::unserialize(Checkpoint *cp, const string &section)
211{
212    UNSERIALIZE_SCALAR(size);
213    UNSERIALIZE_SCALAR(nlu);
214
215    for (int i = 0; i < size; i++) {
216        table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
217        if (table[i].V0 || table[i].V1) {
218            lookupTable.insert(make_pair(table[i].VPN, i));
219        }
220    }
221}
222
223void
224TLB::regStats()
225{
226    read_hits
227        .name(name() + ".read_hits")
228        .desc("DTB read hits")
229        ;
230
231    read_misses
232        .name(name() + ".read_misses")
233        .desc("DTB read misses")
234        ;
235
236
237    read_accesses
238        .name(name() + ".read_accesses")
239        .desc("DTB read accesses")
240        ;
241
242    write_hits
243        .name(name() + ".write_hits")
244        .desc("DTB write hits")
245        ;
246
247    write_misses
248        .name(name() + ".write_misses")
249        .desc("DTB write misses")
250        ;
251
252
253    write_accesses
254        .name(name() + ".write_accesses")
255        .desc("DTB write accesses")
256        ;
257
258    hits
259        .name(name() + ".hits")
260        .desc("DTB hits")
261        ;
262
263    misses
264        .name(name() + ".misses")
265        .desc("DTB misses")
266        ;
267
268    invalids
269        .name(name() + ".invalids")
270        .desc("DTB access violations")
271        ;
272
273    accesses
274        .name(name() + ".accesses")
275        .desc("DTB accesses")
276        ;
277
278    hits = read_hits + write_hits;
279    misses = read_misses + write_misses;
280    accesses = read_accesses + write_accesses;
281}
282
283Fault
284TLB::translateInst(RequestPtr req, ThreadContext *tc)
285{
286    // Instruction accesses must be word-aligned
287    if (req->getVaddr() & 0x3) {
288        DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
289                req->getSize());
290        return new AlignmentFault();
291    }
292
293     Process * p = tc->getProcessPtr();
294
295     Fault fault = p->pTable->translate(req);
296    if (fault != NoFault)
297        return fault;
298
299    return NoFault;
300}
301
302Fault
303TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
304{
305    Process * p = tc->getProcessPtr();
306
307    Fault fault = p->pTable->translate(req);
308    if (fault != NoFault)
309        return fault;
310
311    return NoFault;
312}
313
314Fault
315TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
316{
317#if !FULL_SYSTEM
318    if (mode == Execute)
319        return translateInst(req, tc);
320    else
321        return translateData(req, tc, mode == Write);
322#else
323  fatal("translate atomic not yet implemented\n");
324#endif
325}
326
327void
328TLB::translateTiming(RequestPtr req, ThreadContext *tc,
329                     Translation *translation, Mode mode)
330{
331    assert(translation);
332    translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
333}
334
335PowerISA::PTE &
336TLB::index(bool advance)
337{
338    PowerISA::PTE *pte = &table[nlu];
339
340    if (advance)
341        nextnlu();
342
343    return *pte;
344}
345
346PowerISA::TLB *
347PowerTLBParams::create()
348{
349    return new PowerISA::TLB(this);
350}
351