registers.hh revision 7649
16691Stjones1@inf.ed.ac.uk/* 26691Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 36691Stjones1@inf.ed.ac.uk * All rights reserved. 46691Stjones1@inf.ed.ac.uk * 56691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 66691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 76691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 86691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 96691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 106691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 116691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 126691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 136691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 146691Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 156691Stjones1@inf.ed.ac.uk * 166691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276691Stjones1@inf.ed.ac.uk * 286691Stjones1@inf.ed.ac.uk * Authors: Timothy M. Jones 296691Stjones1@inf.ed.ac.uk */ 306691Stjones1@inf.ed.ac.uk 316691Stjones1@inf.ed.ac.uk#ifndef __ARCH_POWER_REGISTERS_HH__ 326691Stjones1@inf.ed.ac.uk#define __ARCH_POWER_REGISTERS_HH__ 336691Stjones1@inf.ed.ac.uk 346691Stjones1@inf.ed.ac.uk#include "arch/power/max_inst_regs.hh" 356691Stjones1@inf.ed.ac.uk#include "arch/power/miscregs.hh" 366691Stjones1@inf.ed.ac.uk 376691Stjones1@inf.ed.ac.uknamespace PowerISA { 386691Stjones1@inf.ed.ac.uk 396691Stjones1@inf.ed.ac.ukusing PowerISAInst::MaxInstSrcRegs; 406691Stjones1@inf.ed.ac.ukusing PowerISAInst::MaxInstDestRegs; 416691Stjones1@inf.ed.ac.uk 426691Stjones1@inf.ed.ac.uktypedef uint8_t RegIndex; 436691Stjones1@inf.ed.ac.uk 446691Stjones1@inf.ed.ac.uktypedef uint64_t IntReg; 456691Stjones1@inf.ed.ac.uk 466691Stjones1@inf.ed.ac.uk// Floating point register file entry type 476691Stjones1@inf.ed.ac.uktypedef uint64_t FloatRegBits; 486691Stjones1@inf.ed.ac.uktypedef double FloatReg; 496691Stjones1@inf.ed.ac.uktypedef uint64_t MiscReg; 506691Stjones1@inf.ed.ac.uk 516691Stjones1@inf.ed.ac.uk// Constants Related to the number of registers 526691Stjones1@inf.ed.ac.ukconst int NumIntArchRegs = 32; 536691Stjones1@inf.ed.ac.uk 546691Stjones1@inf.ed.ac.uk// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR 556691Stjones1@inf.ed.ac.uk// and zero register, which doesn't actually exist but needs a number 566691Stjones1@inf.ed.ac.ukconst int NumIntSpecialRegs = 9; 576691Stjones1@inf.ed.ac.ukconst int NumFloatArchRegs = 32; 586691Stjones1@inf.ed.ac.ukconst int NumFloatSpecialRegs = 0; 596691Stjones1@inf.ed.ac.ukconst int NumInternalProcRegs = 0; 606691Stjones1@inf.ed.ac.uk 616691Stjones1@inf.ed.ac.ukconst int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 626691Stjones1@inf.ed.ac.ukconst int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 636691Stjones1@inf.ed.ac.ukconst int NumMiscRegs = NUM_MISCREGS; 646691Stjones1@inf.ed.ac.uk 656691Stjones1@inf.ed.ac.uk// Semantically meaningful register indices 666691Stjones1@inf.ed.ac.ukconst int ReturnValueReg = 3; 676691Stjones1@inf.ed.ac.ukconst int ArgumentReg0 = 3; 686691Stjones1@inf.ed.ac.ukconst int ArgumentReg1 = 4; 696691Stjones1@inf.ed.ac.ukconst int ArgumentReg2 = 5; 706691Stjones1@inf.ed.ac.ukconst int ArgumentReg3 = 6; 716691Stjones1@inf.ed.ac.ukconst int ArgumentReg4 = 7; 726691Stjones1@inf.ed.ac.ukconst int FramePointerReg = 31; 736691Stjones1@inf.ed.ac.ukconst int StackPointerReg = 1; 746691Stjones1@inf.ed.ac.uk 756691Stjones1@inf.ed.ac.uk// There isn't one in Power, but we need to define one somewhere 766691Stjones1@inf.ed.ac.ukconst int ZeroReg = NumIntRegs - 1; 776691Stjones1@inf.ed.ac.uk 786691Stjones1@inf.ed.ac.ukconst int SyscallNumReg = 0; 796691Stjones1@inf.ed.ac.ukconst int SyscallPseudoReturnReg = 3; 806691Stjones1@inf.ed.ac.ukconst int SyscallSuccessReg = 3; 816691Stjones1@inf.ed.ac.uk 826691Stjones1@inf.ed.ac.uk// These help enumerate all the registers for dependence tracking. 836691Stjones1@inf.ed.ac.ukconst int FP_Base_DepTag = NumIntRegs; 846691Stjones1@inf.ed.ac.ukconst int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 857649Sminkyu.jeong@arm.comconst int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs; 866691Stjones1@inf.ed.ac.uk 876691Stjones1@inf.ed.ac.uktypedef union { 886691Stjones1@inf.ed.ac.uk IntReg intreg; 896691Stjones1@inf.ed.ac.uk FloatReg fpreg; 906691Stjones1@inf.ed.ac.uk MiscReg ctrlreg; 916691Stjones1@inf.ed.ac.uk} AnyReg; 926691Stjones1@inf.ed.ac.uk 936691Stjones1@inf.ed.ac.ukenum MiscIntRegNums { 946691Stjones1@inf.ed.ac.uk INTREG_CR = NumIntArchRegs, 956691Stjones1@inf.ed.ac.uk INTREG_XER, 966691Stjones1@inf.ed.ac.uk INTREG_LR, 976691Stjones1@inf.ed.ac.uk INTREG_CTR, 986691Stjones1@inf.ed.ac.uk INTREG_FPSCR, 996691Stjones1@inf.ed.ac.uk INTREG_RSV, 1006691Stjones1@inf.ed.ac.uk INTREG_RSV_LEN, 1016691Stjones1@inf.ed.ac.uk INTREG_RSV_ADDR 1026691Stjones1@inf.ed.ac.uk}; 1036691Stjones1@inf.ed.ac.uk 1046691Stjones1@inf.ed.ac.uk} // PowerISA namespace 1056691Stjones1@inf.ed.ac.uk 1066691Stjones1@inf.ed.ac.uk#endif // __ARCH_POWER_REGISTERS_HH__ 107