operands.isa revision 7791 
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2
3// Copyright (c) 2009 The University of Edinburgh
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29// Authors: Timothy M. Jones
30
31def operand_types {{
32    'sb' : ('signed int', 8),
33    'ub' : ('unsigned int', 8),
34    'sh' : ('signed int', 16),
35    'uh' : ('unsigned int', 16),
36    'sw' : ('signed int', 32),
37    'uw' : ('unsigned int', 32),
38    'sq' : ('signed int', 64),
39    'uq' : ('unsigned int', 64),
40    'sf' : ('float', 32),
41    'df' : ('float', 64)
42}};
43
44def operands {{
45    # General Purpose Integer Reg Operands
46    'Ra': ('IntReg', 'uw', 'RA', 'IsInteger', 1),
47    'Rb': ('IntReg', 'uw', 'RB', 'IsInteger', 2),
48    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
49    'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 4),
50
51    # General Purpose Floating Point Reg Operands
52    'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
53    'Fb': ('FloatReg', 'df', 'FRB', 'IsFloating', 2),
54    'Fc': ('FloatReg', 'df', 'FRC', 'IsFloating', 3),
55    'Fs': ('FloatReg', 'df', 'FRS', 'IsFloating', 4),
56    'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
57
58    # Memory Operand
59    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
60
61    # Program counter and next
62    'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
63    'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
64
65    # Control registers
66    'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
67    'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
68    'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9),
69    'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
70
71    # Setting as IntReg so things are stored as an integer, not double
72    'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),
73
74    # Registers for linked loads and stores
75    'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
76    'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
77    'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9),
78
79    # Hack for non-full-system syscall emulation
80    'R0':  ('IntReg', 'uw', '0', None, 1),
81}};
82