fp.isa revision 6691:cd68b6ecd68d
14019Sstever@eecs.umich.edu// -*- mode:c++ -*- 23187Srdreslin@umich.edu 33187Srdreslin@umich.edu// Copyright (c) 2009 The University of Edinburgh 43187Srdreslin@umich.edu// All rights reserved. 53187Srdreslin@umich.edu// 63187Srdreslin@umich.edu// Redistribution and use in source and binary forms, with or without 73187Srdreslin@umich.edu// modification, are permitted provided that the following conditions are 83187Srdreslin@umich.edu// met: redistributions of source code must retain the above copyright 93187Srdreslin@umich.edu// notice, this list of conditions and the following disclaimer; 103187Srdreslin@umich.edu// redistributions in binary form must reproduce the above copyright 113187Srdreslin@umich.edu// notice, this list of conditions and the following disclaimer in the 123187Srdreslin@umich.edu// documentation and/or other materials provided with the distribution; 133187Srdreslin@umich.edu// neither the name of the copyright holders nor the names of its 143187Srdreslin@umich.edu// contributors may be used to endorse or promote products derived from 153187Srdreslin@umich.edu// this software without specific prior written permission. 163187Srdreslin@umich.edu// 173187Srdreslin@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 183187Srdreslin@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 193187Srdreslin@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 203187Srdreslin@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 213187Srdreslin@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 223187Srdreslin@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 233187Srdreslin@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 243187Srdreslin@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 253187Srdreslin@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 263187Srdreslin@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 273187Srdreslin@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 283187Srdreslin@umich.edu// 293187Srdreslin@umich.edu// Authors: Timothy M. Jones 303187Srdreslin@umich.edu 319321Sandreas.hansson@arm.com//////////////////////////////////////////////////////////////////// 329321Sandreas.hansson@arm.com// 333187Srdreslin@umich.edu// Floating Point operate instructions 343196Srdreslin@umich.edu// 353196Srdreslin@umich.edu 369793Sakash.bagdia@arm.com 373187Srdreslin@umich.edulet {{ 383187Srdreslin@umich.edu 3910688Sandreas.hansson@arm.com readFPSCRCode = 'Fpscr fpscr = FPSCR;' 408931Sandreas.hansson@arm.com 4110405Sandreas.hansson@arm.com computeCR1Code = ''' 429827Sakash.bagdia@arm.com Cr cr = CR; 439827Sakash.bagdia@arm.com cr.cr1 = (fpscr.fx << 3) | (fpscr.fex << 2) | 449827Sakash.bagdia@arm.com (fpscr.vx << 1) | fpscr.ox; 459827Sakash.bagdia@arm.com CR = cr; 463187Srdreslin@umich.edu ''' 479793Sakash.bagdia@arm.com 489793Sakash.bagdia@arm.com}}; 499827Sakash.bagdia@arm.com 509827Sakash.bagdia@arm.com// Primary format for floating point operate instructions: 519793Sakash.bagdia@arm.comdef format FloatOp(code, inst_flags = []) {{ 5210405Sandreas.hansson@arm.com iop = InstObjParams(name, Name, 'FloatOp', 539793Sakash.bagdia@arm.com {"code": code}, 548839Sandreas.hansson@arm.com inst_flags) 553187Srdreslin@umich.edu header_output = BasicDeclare.subst(iop) 563187Srdreslin@umich.edu decoder_output = BasicConstructor.subst(iop) 578839Sandreas.hansson@arm.com decode_block = BasicDecode.subst(iop) 583187Srdreslin@umich.edu exec_output = BasicExecute.subst(iop) 593187Srdreslin@umich.edu}}; 603187Srdreslin@umich.edu 619793Sakash.bagdia@arm.com// Floating point operations that compute the CR1 code if RC is set. No other 629793Sakash.bagdia@arm.com// special registers are touched using these operations. 639321Sandreas.hansson@arm.comdef format FloatRCCheckOp(code, inst_flags = []) {{ 6410688Sandreas.hansson@arm.com 658839Sandreas.hansson@arm.com # Code when Rc is set 663187Srdreslin@umich.edu code_rc1 = code + readFPSCRCode + computeCR1Code 678839Sandreas.hansson@arm.com 688706Sandreas.hansson@arm.com # Generate the first class 693187Srdreslin@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 708839Sandreas.hansson@arm.com GenAluOp(name, Name, 'FloatOp', code, inst_flags, 713187Srdreslin@umich.edu CheckRcDecode, BasicConstructor) 723187Srdreslin@umich.edu 733187Srdreslin@umich.edu # Generate the second class 743187Srdreslin@umich.edu (header_output_rc1, decoder_output_rc1, _, exec_output_rc1) = \ 753187Srdreslin@umich.edu GenAluOp(name, Name + 'RcSet', 'FloatOp', code_rc1, inst_flags, 763187Srdreslin@umich.edu CheckRcDecode, IntRcConstructor) 778801Sgblack@eecs.umich.edu 783187Srdreslin@umich.edu # Finally, add to the other outputs 793257Srdreslin@umich.edu header_output += header_output_rc1 80 decoder_output += decoder_output_rc1 81 exec_output += exec_output_rc1 82}}; 83 84// Floating point elementary arithmetic operations. Besides having two 85// versions of each instruction for when Rc is set or not, we also have 86// to alter lots of special registers depending on the result of the 87// operation. The result is always in Ft.sf. 88def format FloatArithOp(code, inst_flags = []) {{ 89 90 # Code when Rc is set 91 code_rc1 = code + readFPSCRCode + computeCR1Code 92 93 # Generate the first class 94 (header_output, decoder_output, decode_block, exec_output) = \ 95 GenAluOp(name, Name, 'FloatOp', code, inst_flags, 96 CheckRcDecode, BasicConstructor) 97 98 # Generate the second class 99 (header_output_rc1, decoder_output_rc1, _, exec_output_rc1) = \ 100 GenAluOp(name, Name + 'RcSet', 'FloatOp', code_rc1, inst_flags, 101 CheckRcDecode, IntRcConstructor) 102 103 # Finally, add to the other outputs 104 header_output += header_output_rc1 105 decoder_output += decoder_output_rc1 106 exec_output += exec_output_rc1 107}}; 108 109// Floating point rounding and conversion operations. Besides having two 110// versions of each instruction for when Rc is set or not, we also have 111// to alter lots of special registers depending on the result of the 112// operation. The result is always in Ft.sf. 113def format FloatConvertOp(code, inst_flags = []) {{ 114 115 # Code when Rc is set 116 code_rc1 = code + readFPSCRCode + computeCR1Code 117 118 # Generate the first class 119 (header_output, decoder_output, decode_block, exec_output) = \ 120 GenAluOp(name, Name, 'FloatOp', code, inst_flags, 121 CheckRcDecode, BasicConstructor) 122 123 # Generate the second class 124 (header_output_rc1, decoder_output_rc1, _, exec_output_rc1) = \ 125 GenAluOp(name, Name + 'RcSet', 'FloatOp', code_rc1, inst_flags, 126 CheckRcDecode, IntRcConstructor) 127 128 # Finally, add to the other outputs 129 header_output += header_output_rc1 130 decoder_output += decoder_output_rc1 131 exec_output += exec_output_rc1 132}}; 133