decoder.isa revision 7720:65d338a8dba4
1// -*- mode:c++ -*- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Timothy M. Jones 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual Power ISA decoder 34// ------------------------------ 35// 36// I've used the Power ISA Book I v2.06 for instruction formats, 37// opcode numbers, register names, etc. 38// 39decode OPCODE default Unknown::unknown() { 40 41 format IntImmOp { 42 10: cmpli({{ 43 Xer xer = XER; 44 uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so); 45 CR = insertCRField(CR, BF, cr); 46 }}); 47 11: cmpi({{ 48 Xer xer = XER; 49 uint32_t cr = makeCRField(Ra.sw, (int32_t)imm, xer.so); 50 CR = insertCRField(CR, BF, cr); 51 }}); 52 } 53 54 // Some instructions use bits 21 - 30, others 22 - 30. We have to use 55 // the larger size to account for all opcodes. For those that use the 56 // smaller value, the OE bit is bit 21. Therefore, we have two versions 57 // of each instruction: 1 with OE set, the other without. For an 58 // example see 'add' and 'addo'. 59 31: decode XO_XO { 60 61 // These instructions can all be reduced to the form 62 // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2 63 // (and, if necessary, CA) definitions and let the python script 64 // deal with setting things up correctly. We also give flags to 65 // say which control registers to set. 66 format IntSumOp { 67 266: add({{ Ra }}, {{ Rb }}); 68 40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }}); 69 10: addc({{ Ra }}, {{ Rb }}, 70 computeCA = true); 71 8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }}, 72 true); 73 104: neg({{ ~Ra }}, {{ 1 }}); 74 138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }}, 75 true); 76 234: addme({{ Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }}, 77 true); 78 136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }}, 79 true); 80 232: subfme({{ ~Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }}, 81 true); 82 202: addze({{ Ra }}, {{ xer.ca }}, 83 computeCA = true); 84 200: subfze({{ ~Ra }}, {{ xer.ca }}, 85 computeCA = true); 86 } 87 88 // Arithmetic instructions all use source registers Ra and Rb, 89 // with destination register Rt. 90 format IntArithOp { 91 75: mulhw({{ int64_t prod = Ra.sq * Rb.sq; Rt = prod >> 32; }}); 92 11: mulhwu({{ uint64_t prod = Ra.uq * Rb.uq; Rt = prod >> 32; }}); 93 235: mullw({{ int64_t prod = Ra.sq * Rb.sq; Rt = prod; }}); 94 747: mullwo({{ int64_t src1 = Ra.sq; int64_t src2 = Rb; int64_t prod = src1 * src2; Rt = prod; }}, 95 true); 96 97 491: divw({{ 98 int32_t src1 = Ra.sw; 99 int32_t src2 = Rb.sw; 100 if ((src1 != 0x80000000 || src2 != 0xffffffff) 101 && src2 != 0) { 102 Rt = src1 / src2; 103 } else { 104 Rt = 0; 105 } 106 }}); 107 108 1003: divwo({{ 109 int32_t src1 = Ra.sw; 110 int32_t src2 = Rb.sw; 111 if ((src1 != 0x80000000 || src2 != 0xffffffff) 112 && src2 != 0) { 113 Rt = src1 / src2; 114 } else { 115 Rt = 0; 116 divSetOV = true; 117 } 118 }}, 119 true); 120 121 459: divwu({{ 122 uint32_t src1 = Ra.sw; 123 uint32_t src2 = Rb.sw; 124 if (src2 != 0) { 125 Rt = src1 / src2; 126 } else { 127 Rt = 0; 128 } 129 }}); 130 131 971: divwuo({{ 132 uint32_t src1 = Ra.sw; 133 uint32_t src2 = Rb.sw; 134 if (src2 != 0) { 135 Rt = src1 / src2; 136 } else { 137 Rt = 0; 138 divSetOV = true; 139 } 140 }}, 141 true); 142 } 143 144 // Integer logic instructions use source registers Rs and Rb, 145 // with destination register Ra. 146 format IntLogicOp { 147 28: and({{ Ra = Rs & Rb; }}); 148 316: xor({{ Ra = Rs ^ Rb; }}); 149 476: nand({{ Ra = ~(Rs & Rb); }}); 150 444: or({{ Ra = Rs | Rb; }}); 151 124: nor({{ Ra = ~(Rs | Rb); }}); 152 60: andc({{ Ra = Rs & ~Rb; }}); 153 954: extsb({{ Ra = sext<8>(Rs); }}); 154 284: eqv({{ Ra = ~(Rs ^ Rb); }}); 155 412: orc({{ Ra = Rs | ~Rb; }}); 156 922: extsh({{ Ra = sext<16>(Rs); }}); 157 26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }}); 158 508: cmpb({{ 159 uint32_t val = 0; 160 for (int n = 0; n < 32; n += 8) { 161 if(bits(Rs, n, n+7) == bits(Rb, n, n+7)) { 162 val = insertBits(val, n, n+7, 0xff); 163 } 164 } 165 Ra = val; 166 }}); 167 168 24: slw({{ 169 if (Rb & 0x20) { 170 Ra = 0; 171 } else { 172 Ra = Rs << (Rb & 0x1f); 173 } 174 }}); 175 176 536: srw({{ 177 if (Rb & 0x20) { 178 Ra = 0; 179 } else { 180 Ra = Rs >> (Rb & 0x1f); 181 } 182 }}); 183 184 792: sraw({{ 185 bool shiftSetCA = false; 186 int32_t s = Rs; 187 if (Rb == 0) { 188 Ra = Rs; 189 shiftSetCA = true; 190 } else if (Rb & 0x20) { 191 if (s < 0) { 192 Ra = (uint32_t)-1; 193 if (s & 0x7fffffff) { 194 shiftSetCA = true; 195 } else { 196 shiftSetCA = false; 197 } 198 } else { 199 Ra = 0; 200 shiftSetCA = false; 201 } 202 } else { 203 Ra = s >> (Rb & 0x1f); 204 if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) { 205 shiftSetCA = true; 206 } else { 207 shiftSetCA = false; 208 } 209 } 210 Xer xer1 = XER; 211 if (shiftSetCA) { 212 xer1.ca = 1; 213 } else { 214 xer1.ca = 0; 215 } 216 XER = xer1; 217 }}); 218 } 219 220 // Integer logic instructions with a shift value. 221 format IntShiftOp { 222 824: srawi({{ 223 bool shiftSetCA = false; 224 if (sh == 0) { 225 Ra = Rs; 226 shiftSetCA = false; 227 } else { 228 int32_t s = Rs; 229 Ra = s >> sh; 230 if (s < 0 && (s << (32 - sh)) != 0) { 231 shiftSetCA = true; 232 } else { 233 shiftSetCA = false; 234 } 235 } 236 Xer xer1 = XER; 237 if (shiftSetCA) { 238 xer1.ca = 1; 239 } else { 240 xer1.ca = 0; 241 } 242 XER = xer1; 243 }}); 244 } 245 246 // Generic integer format instructions. 247 format IntOp { 248 0: cmp({{ 249 Xer xer = XER; 250 uint32_t cr = makeCRField(Ra.sw, Rb.sw, xer.so); 251 CR = insertCRField(CR, BF, cr); 252 }}); 253 32: cmpl({{ 254 Xer xer = XER; 255 uint32_t cr = makeCRField(Ra, Rb, xer.so); 256 CR = insertCRField(CR, BF, cr); 257 }}); 258 144: mtcrf({{ 259 uint32_t mask = 0; 260 for (int i = 0; i < 8; ++i) { 261 if (((FXM >> i) & 0x1) == 0x1) { 262 mask |= 0xf << (4 * i); 263 } 264 } 265 CR = (Rs & mask) | (CR & ~mask); 266 }}); 267 19: mfcr({{ Rt = CR; }}); 268 339: decode SPR { 269 0x20: mfxer({{ Rt = XER; }}); 270 0x100: mflr({{ Rt = LR; }}); 271 0x120: mfctr({{ Rt = CTR; }}); 272 } 273 467: decode SPR { 274 0x20: mtxer({{ XER = Rs; }}); 275 0x100: mtlr({{ LR = Rs; }}); 276 0x120: mtctr({{ CTR = Rs; }}); 277 } 278 } 279 280 // All loads with an index register. The non-update versions 281 // all use the value 0 if Ra == R0, not the value contained in 282 // R0. Others update Ra with the effective address. In all cases, 283 // Ra and Rb are source registers, Rt is the destintation. 284 format LoadIndexOp { 285 87: lbzx({{ Rt = Mem.ub; }}); 286 279: lhzx({{ Rt = Mem.uh; }}); 287 343: lhax({{ Rt = Mem.sh; }}); 288 23: lwzx({{ Rt = Mem; }}); 289 341: lwax({{ Rt = Mem.sw; }}); 290 20: lwarx({{ Rt = Mem.sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }}); 291 535: lfsx({{ Ft.sf = Mem.sf; }}); 292 599: lfdx({{ Ft = Mem.df; }}); 293 855: lfiwax({{ Ft.uw = Mem; }}); 294 } 295 296 format LoadIndexUpdateOp { 297 119: lbzux({{ Rt = Mem.ub; }}); 298 311: lhzux({{ Rt = Mem.uh; }}); 299 375: lhaux({{ Rt = Mem.sh; }}); 300 55: lwzux({{ Rt = Mem; }}); 301 373: lwaux({{ Rt = Mem.sw; }}); 302 567: lfsux({{ Ft.sf = Mem.sf; }}); 303 631: lfdux({{ Ft = Mem.df; }}); 304 } 305 306 format StoreIndexOp { 307 215: stbx({{ Mem.ub = Rs.ub; }}); 308 407: sthx({{ Mem.uh = Rs.uh; }}); 309 151: stwx({{ Mem = Rs; }}); 310 150: stwcx({{ 311 bool store_performed = false; 312 if (Rsv) { 313 if (RsvLen == 4) { 314 if (RsvAddr == EA) { 315 Mem = Rs; 316 store_performed = true; 317 } 318 } 319 } 320 Xer xer = XER; 321 Cr cr = CR; 322 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so); 323 CR = cr; 324 Rsv = 0; 325 }}); 326 663: stfsx({{ Mem.sf = Fs.sf; }}); 327 727: stfdx({{ Mem.df = Fs; }}); 328 983: stfiwx({{ Mem = Fs.uw; }}); 329 } 330 331 format StoreIndexUpdateOp { 332 247: stbux({{ Mem.ub = Rs.ub; }}); 333 439: sthux({{ Mem.uh = Rs.uh; }}); 334 183: stwux({{ Mem = Rs; }}); 335 695: stfsux({{ Mem.sf = Fs.sf; }}); 336 759: stfdux({{ Mem.df = Fs; }}); 337 } 338 339 // These instructions all provide data cache hints 340 format MiscOp { 341 278: dcbt({{ }}); 342 246: dcbtst({{ }}); 343 598: sync({{ }}, [ IsMemBarrier ]); 344 854: eieio({{ }}, [ IsMemBarrier ]); 345 } 346 } 347 348 format IntImmArithCheckRaOp { 349 14: addi({{ Rt = Ra + imm; }}, 350 {{ Rt = imm }}); 351 15: addis({{ Rt = Ra + (imm << 16); }}, 352 {{ Rt = imm << 16; }}); 353 } 354 355 format IntImmArithOp { 356 12: addic({{ uint32_t src = Ra; Rt = src + imm; }}, 357 [computeCA]); 358 13: addic_({{ uint32_t src = Ra; Rt = src + imm; }}, 359 [computeCA, computeCR0]); 360 8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }}, 361 [computeCA]); 362 7: mulli({{ 363 int32_t src = Ra.sw; 364 int64_t prod = src * imm; 365 Rt = (uint32_t)prod; 366 }}); 367 } 368 369 format IntImmLogicOp { 370 24: ori({{ Ra = Rs | uimm; }}); 371 25: oris({{ Ra = Rs | (uimm << 16); }}); 372 26: xori({{ Ra = Rs ^ uimm; }}); 373 27: xoris({{ Ra = Rs ^ (uimm << 16); }}); 374 28: andi_({{ Ra = Rs & uimm; }}, 375 true); 376 29: andis_({{ Ra = Rs & (uimm << 16); }}, 377 true); 378 } 379 380 16: decode AA { 381 382 // Conditionally branch relative to PC based on CR and CTR. 383 format BranchPCRelCondCtr { 384 0: bc({{ 385 PowerISA::PCState pc = PCS; 386 pc.npc((uint32_t)(pc.pc() + disp)); 387 PCS = pc; 388 }}); 389 } 390 391 // Conditionally branch to fixed address based on CR and CTR. 392 format BranchNonPCRelCondCtr { 393 1: bca({{ 394 PowerISA::PCState pc = PCS; 395 pc.npc(targetAddr); 396 PCS = pc; 397 }}); 398 } 399 } 400 401 18: decode AA { 402 403 // Unconditionally branch relative to PC. 404 format BranchPCRel { 405 0: b({{ 406 PowerISA::PCState pc = PCS; 407 pc.npc((uint32_t)(pc.pc() + disp)); 408 PCS = pc; 409 }}); 410 } 411 412 // Unconditionally branch to fixed address. 413 format BranchNonPCRel { 414 1: ba({{ 415 PowerISA::PCState pc = PCS; 416 pc.npc(targetAddr); 417 PCS = pc; 418 }}); 419 } 420 } 421 422 19: decode XO_XO { 423 424 // Conditionally branch to address in LR based on CR and CTR. 425 format BranchLrCondCtr { 426 16: bclr({{ 427 PowerISA::PCState pc = PCS; 428 pc.npc(LR & 0xfffffffc); 429 PCS = pc; 430 }}); 431 } 432 433 // Conditionally branch to address in CTR based on CR. 434 format BranchCtrCond { 435 528: bcctr({{ 436 PowerISA::PCState pc = PCS; 437 pc.npc(CTR & 0xfffffffc); 438 PCS = pc; 439 }}); 440 } 441 442 // Condition register manipulation instructions. 443 format CondLogicOp { 444 257: crand({{ 445 uint32_t crBa = bits(CR, 31 - ba); 446 uint32_t crBb = bits(CR, 31 - bb); 447 CR = insertBits(CR, 31 - bt, crBa & crBb); 448 }}); 449 449: cror({{ 450 uint32_t crBa = bits(CR, 31 - ba); 451 uint32_t crBb = bits(CR, 31 - bb); 452 CR = insertBits(CR, 31 - bt, crBa | crBb); 453 }}); 454 255: crnand({{ 455 uint32_t crBa = bits(CR, 31 - ba); 456 uint32_t crBb = bits(CR, 31 - bb); 457 CR = insertBits(CR, 31 - bt, !(crBa & crBb)); 458 }}); 459 193: crxor({{ 460 uint32_t crBa = bits(CR, 31 - ba); 461 uint32_t crBb = bits(CR, 31 - bb); 462 CR = insertBits(CR, 31 - bt, crBa ^ crBb); 463 }}); 464 33: crnor({{ 465 uint32_t crBa = bits(CR, 31 - ba); 466 uint32_t crBb = bits(CR, 31 - bb); 467 CR = insertBits(CR, 31 - bt, !(crBa | crBb)); 468 }}); 469 289: creqv({{ 470 uint32_t crBa = bits(CR, 31 - ba); 471 uint32_t crBb = bits(CR, 31 - bb); 472 CR = insertBits(CR, 31 - bt, crBa == crBb); 473 }}); 474 129: crandc({{ 475 uint32_t crBa = bits(CR, 31 - ba); 476 uint32_t crBb = bits(CR, 31 - bb); 477 CR = insertBits(CR, 31 - bt, crBa & !crBb); 478 }}); 479 417: crorc({{ 480 uint32_t crBa = bits(CR, 31 - ba); 481 uint32_t crBb = bits(CR, 31 - bb); 482 CR = insertBits(CR, 31 - bt, crBa | !crBb); 483 }}); 484 } 485 format CondMoveOp { 486 0: mcrf({{ 487 uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4); 488 CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa); 489 }}); 490 } 491 format MiscOp { 492 150: isync({{ }}, [ IsSerializeAfter ]); 493 } 494 } 495 496 format IntRotateOp { 497 21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }}); 498 23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }}); 499 20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) | (Ra & ~fullMask); }}); 500 } 501 502 format LoadDispOp { 503 34: lbz({{ Rt = Mem.ub; }}); 504 40: lhz({{ Rt = Mem.uh; }}); 505 42: lha({{ Rt = Mem.sh; }}); 506 32: lwz({{ Rt = Mem; }}); 507 58: lwa({{ Rt = Mem.sw; }}, 508 {{ EA = Ra + (disp & 0xfffffffc); }}, 509 {{ EA = disp & 0xfffffffc; }}); 510 48: lfs({{ Ft.sf = Mem.sf; }}); 511 50: lfd({{ Ft = Mem.df; }}); 512 } 513 514 format LoadDispUpdateOp { 515 35: lbzu({{ Rt = Mem.ub; }}); 516 41: lhzu({{ Rt = Mem.uh; }}); 517 43: lhau({{ Rt = Mem.sh; }}); 518 33: lwzu({{ Rt = Mem; }}); 519 49: lfsu({{ Ft.sf = Mem.sf; }}); 520 51: lfdu({{ Ft = Mem.df; }}); 521 } 522 523 format StoreDispOp { 524 38: stb({{ Mem.ub = Rs.ub; }}); 525 44: sth({{ Mem.uh = Rs.uh; }}); 526 36: stw({{ Mem = Rs; }}); 527 52: stfs({{ Mem.sf = Fs.sf; }}); 528 54: stfd({{ Mem.df = Fs; }}); 529 } 530 531 format StoreDispUpdateOp { 532 39: stbu({{ Mem.ub = Rs.ub; }}); 533 45: sthu({{ Mem.uh = Rs.uh; }}); 534 37: stwu({{ Mem = Rs; }}); 535 53: stfsu({{ Mem.sf = Fs.sf; }}); 536 55: stfdu({{ Mem.df = Fs; }}); 537 } 538 539 17: IntOp::sc({{ xc->syscall(R0); }}, 540 [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]); 541 542 format FloatArithOp { 543 59: decode A_XO { 544 21: fadds({{ Ft = Fa + Fb; }}); 545 20: fsubs({{ Ft = Fa - Fb; }}); 546 25: fmuls({{ Ft = Fa * Fc; }}); 547 18: fdivs({{ Ft = Fa / Fb; }}); 548 29: fmadds({{ Ft = (Fa * Fc) + Fb; }}); 549 28: fmsubs({{ Ft = (Fa * Fc) - Fb; }}); 550 31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }}); 551 30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }}); 552 } 553 } 554 555 63: decode A_XO { 556 format FloatArithOp { 557 21: fadd({{ Ft = Fa + Fb; }}); 558 20: fsub({{ Ft = Fa - Fb; }}); 559 25: fmul({{ Ft = Fa * Fc; }}); 560 18: fdiv({{ Ft = Fa / Fb; }}); 561 29: fmadd({{ Ft = (Fa * Fc) + Fb; }}); 562 28: fmsub({{ Ft = (Fa * Fc) - Fb; }}); 563 31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }}); 564 30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }}); 565 } 566 567 default: decode XO_XO { 568 format FloatConvertOp { 569 12: frsp({{ Ft.sf = Fb; }}); 570 15: fctiwz({{ Ft.sw = (int32_t)trunc(Fb); }}); 571 } 572 573 format FloatOp { 574 0: fcmpu({{ 575 uint32_t c = makeCRField(Fa, Fb); 576 Fpscr fpscr = FPSCR; 577 fpscr.fprf.fpcc = c; 578 FPSCR = fpscr; 579 CR = insertCRField(CR, BF, c); 580 }}); 581 } 582 583 format FloatRCCheckOp { 584 72: fmr({{ Ft = Fb; }}); 585 264: fabs({{ 586 Ft.uq = Fb.uq; 587 Ft.uq = insertBits(Ft.uq, 63, 0); }}); 588 136: fnabs({{ 589 Ft.uq = Fb.uq; 590 Ft.uq = insertBits(Ft.uq, 63, 1); }}); 591 40: fneg({{ Ft = -Fb; }}); 592 8: fcpsgn({{ 593 Ft.uq = Fb.uq; 594 Ft.uq = insertBits(Ft.uq, 63, Fa.uq<63:63>); 595 }}); 596 583: mffs({{ Ft.uq = FPSCR; }}); 597 134: mtfsfi({{ 598 FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W)), U_FIELD); 599 }}); 600 711: mtfsf({{ 601 if (L == 1) { FPSCR = Fb.uq; } 602 else { 603 for (int i = 0; i < 8; ++i) { 604 if (bits(FLM, i) == 1) { 605 int k = 4 * (i + (8 * (1 - W))); 606 FPSCR = insertBits(FPSCR, k, k + 3, 607 bits(Fb.uq, k, k + 3)); 608 } 609 } 610 } 611 }}); 612 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }}); 613 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }}); 614 } 615 } 616 } 617} 618