isa.hh revision 7811
16691Stjones1@inf.ed.ac.uk/* 26691Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The Regents of The University of Michigan 36691Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 46691Stjones1@inf.ed.ac.uk * All rights reserved. 56691Stjones1@inf.ed.ac.uk * 66691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 76691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 86691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 96691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 106691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 116691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 126691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 136691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 146691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 156691Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 166691Stjones1@inf.ed.ac.uk * 176691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286691Stjones1@inf.ed.ac.uk * 296691Stjones1@inf.ed.ac.uk * Authors: Gabe Black 306691Stjones1@inf.ed.ac.uk * Timothy M. Jones 316691Stjones1@inf.ed.ac.uk */ 326691Stjones1@inf.ed.ac.uk 336691Stjones1@inf.ed.ac.uk#ifndef __ARCH_POWER_ISA_HH__ 346691Stjones1@inf.ed.ac.uk#define __ARCH_POWER_ISA_HH__ 356691Stjones1@inf.ed.ac.uk 366691Stjones1@inf.ed.ac.uk#include "arch/power/registers.hh" 376691Stjones1@inf.ed.ac.uk#include "arch/power/types.hh" 386691Stjones1@inf.ed.ac.uk#include "base/misc.hh" 396691Stjones1@inf.ed.ac.uk 406691Stjones1@inf.ed.ac.ukclass ThreadContext; 416691Stjones1@inf.ed.ac.ukclass Checkpoint; 426691Stjones1@inf.ed.ac.ukclass EventManager; 436691Stjones1@inf.ed.ac.uk 446691Stjones1@inf.ed.ac.uknamespace PowerISA 456691Stjones1@inf.ed.ac.uk{ 466691Stjones1@inf.ed.ac.uk 476691Stjones1@inf.ed.ac.ukclass ISA 486691Stjones1@inf.ed.ac.uk{ 496691Stjones1@inf.ed.ac.uk protected: 506691Stjones1@inf.ed.ac.uk MiscReg dummy; 516691Stjones1@inf.ed.ac.uk MiscReg miscRegs[NumMiscRegs]; 526691Stjones1@inf.ed.ac.uk 536691Stjones1@inf.ed.ac.uk public: 546691Stjones1@inf.ed.ac.uk void 556691Stjones1@inf.ed.ac.uk clear() 566691Stjones1@inf.ed.ac.uk { 576691Stjones1@inf.ed.ac.uk } 586691Stjones1@inf.ed.ac.uk 596691Stjones1@inf.ed.ac.uk MiscReg 606691Stjones1@inf.ed.ac.uk readMiscRegNoEffect(int misc_reg) 616691Stjones1@inf.ed.ac.uk { 626691Stjones1@inf.ed.ac.uk fatal("Power does not currently have any misc regs defined\n"); 636691Stjones1@inf.ed.ac.uk return dummy; 646691Stjones1@inf.ed.ac.uk } 656691Stjones1@inf.ed.ac.uk 666691Stjones1@inf.ed.ac.uk MiscReg 676691Stjones1@inf.ed.ac.uk readMiscReg(int misc_reg, ThreadContext *tc) 686691Stjones1@inf.ed.ac.uk { 696691Stjones1@inf.ed.ac.uk fatal("Power does not currently have any misc regs defined\n"); 706691Stjones1@inf.ed.ac.uk return dummy; 716691Stjones1@inf.ed.ac.uk } 726691Stjones1@inf.ed.ac.uk 736691Stjones1@inf.ed.ac.uk void 746691Stjones1@inf.ed.ac.uk setMiscRegNoEffect(int misc_reg, const MiscReg &val) 756691Stjones1@inf.ed.ac.uk { 766691Stjones1@inf.ed.ac.uk fatal("Power does not currently have any misc regs defined\n"); 776691Stjones1@inf.ed.ac.uk } 786691Stjones1@inf.ed.ac.uk 796691Stjones1@inf.ed.ac.uk void 806691Stjones1@inf.ed.ac.uk setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 816691Stjones1@inf.ed.ac.uk { 826691Stjones1@inf.ed.ac.uk fatal("Power does not currently have any misc regs defined\n"); 836691Stjones1@inf.ed.ac.uk } 846691Stjones1@inf.ed.ac.uk 856691Stjones1@inf.ed.ac.uk int 866691Stjones1@inf.ed.ac.uk flattenIntIndex(int reg) 876691Stjones1@inf.ed.ac.uk { 886691Stjones1@inf.ed.ac.uk return reg; 896691Stjones1@inf.ed.ac.uk } 906691Stjones1@inf.ed.ac.uk 916691Stjones1@inf.ed.ac.uk int 926691Stjones1@inf.ed.ac.uk flattenFloatIndex(int reg) 936691Stjones1@inf.ed.ac.uk { 946691Stjones1@inf.ed.ac.uk return reg; 956691Stjones1@inf.ed.ac.uk } 966691Stjones1@inf.ed.ac.uk 976691Stjones1@inf.ed.ac.uk void 986691Stjones1@inf.ed.ac.uk serialize(EventManager *em, std::ostream &os) 996691Stjones1@inf.ed.ac.uk { 1006691Stjones1@inf.ed.ac.uk } 1016691Stjones1@inf.ed.ac.uk 1026691Stjones1@inf.ed.ac.uk void 1036691Stjones1@inf.ed.ac.uk unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) 1046691Stjones1@inf.ed.ac.uk { 1056691Stjones1@inf.ed.ac.uk } 1066691Stjones1@inf.ed.ac.uk 1076691Stjones1@inf.ed.ac.uk ISA() 1086691Stjones1@inf.ed.ac.uk { 1096691Stjones1@inf.ed.ac.uk clear(); 1106691Stjones1@inf.ed.ac.uk } 1116691Stjones1@inf.ed.ac.uk}; 1126691Stjones1@inf.ed.ac.uk 1137811Ssteve.reinhardt@amd.com} // namespace PowerISA 1146691Stjones1@inf.ed.ac.uk 1156691Stjones1@inf.ed.ac.uk#endif // __ARCH_POWER_ISA_HH__ 116