decoder.hh revision 9024
15132Sgblack@eecs.umich.edu/* 25132Sgblack@eecs.umich.edu * Copyright (c) 2012 Google 35132Sgblack@eecs.umich.edu * All rights reserved. 45132Sgblack@eecs.umich.edu * 55132Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65132Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75132Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85132Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95132Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105132Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115132Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125132Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135132Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145132Sgblack@eecs.umich.edu * this software without specific prior written permission. 155132Sgblack@eecs.umich.edu * 165132Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175132Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185132Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195132Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205132Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215132Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225132Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235132Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245132Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255132Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265132Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275132Sgblack@eecs.umich.edu * 285132Sgblack@eecs.umich.edu * Authors: Gabe Black 295132Sgblack@eecs.umich.edu */ 305132Sgblack@eecs.umich.edu 315132Sgblack@eecs.umich.edu#ifndef __ARCH_POWER_DECODER_HH__ 325132Sgblack@eecs.umich.edu#define __ARCH_POWER_DECODER_HH__ 335132Sgblack@eecs.umich.edu 345132Sgblack@eecs.umich.edu#include "arch/generic/decode_cache.hh" 355132Sgblack@eecs.umich.edu#include "arch/types.hh" 365132Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 375132Sgblack@eecs.umich.edu 385132Sgblack@eecs.umich.educlass ThreadContext; 395132Sgblack@eecs.umich.edu 405132Sgblack@eecs.umich.edunamespace PowerISA 415132Sgblack@eecs.umich.edu{ 425132Sgblack@eecs.umich.edu 435132Sgblack@eecs.umich.educlass Decoder 445132Sgblack@eecs.umich.edu{ 455132Sgblack@eecs.umich.edu protected: 465132Sgblack@eecs.umich.edu ThreadContext * tc; 475132Sgblack@eecs.umich.edu 485132Sgblack@eecs.umich.edu // The extended machine instruction being generated 495132Sgblack@eecs.umich.edu ExtMachInst emi; 505132Sgblack@eecs.umich.edu bool instDone; 515132Sgblack@eecs.umich.edu 525132Sgblack@eecs.umich.edu public: 535132Sgblack@eecs.umich.edu Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) 545132Sgblack@eecs.umich.edu { 555132Sgblack@eecs.umich.edu } 565132Sgblack@eecs.umich.edu 575132Sgblack@eecs.umich.edu ThreadContext * 585132Sgblack@eecs.umich.edu getTC() 595132Sgblack@eecs.umich.edu { 605132Sgblack@eecs.umich.edu return tc; 615132Sgblack@eecs.umich.edu } 625132Sgblack@eecs.umich.edu 635132Sgblack@eecs.umich.edu void 645132Sgblack@eecs.umich.edu setTC(ThreadContext * _tc) 655132Sgblack@eecs.umich.edu { 665132Sgblack@eecs.umich.edu tc = _tc; 675132Sgblack@eecs.umich.edu } 685132Sgblack@eecs.umich.edu 695132Sgblack@eecs.umich.edu void 705132Sgblack@eecs.umich.edu process() 715334Sgblack@eecs.umich.edu { 725334Sgblack@eecs.umich.edu } 735334Sgblack@eecs.umich.edu 745334Sgblack@eecs.umich.edu void 755334Sgblack@eecs.umich.edu reset() 765334Sgblack@eecs.umich.edu { 775334Sgblack@eecs.umich.edu instDone = false; 785334Sgblack@eecs.umich.edu } 795132Sgblack@eecs.umich.edu 805132Sgblack@eecs.umich.edu // Use this to give data to the predecoder. This should be used 815132Sgblack@eecs.umich.edu // when there is control flow. 825132Sgblack@eecs.umich.edu void 835132Sgblack@eecs.umich.edu moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 845132Sgblack@eecs.umich.edu { 855132Sgblack@eecs.umich.edu emi = inst; 865132Sgblack@eecs.umich.edu instDone = true; 875132Sgblack@eecs.umich.edu } 885132Sgblack@eecs.umich.edu 895132Sgblack@eecs.umich.edu // Use this to give data to the predecoder. This should be used 905299Sgblack@eecs.umich.edu // when instructions are executed in order. 915299Sgblack@eecs.umich.edu void 925299Sgblack@eecs.umich.edu moreBytes(MachInst machInst) 935299Sgblack@eecs.umich.edu { 945132Sgblack@eecs.umich.edu moreBytes(0, 0, machInst); 955132Sgblack@eecs.umich.edu } 965334Sgblack@eecs.umich.edu 975334Sgblack@eecs.umich.edu bool 985334Sgblack@eecs.umich.edu needMoreBytes() 995334Sgblack@eecs.umich.edu { 1005334Sgblack@eecs.umich.edu return true; 1015132Sgblack@eecs.umich.edu } 1025132Sgblack@eecs.umich.edu 1035132Sgblack@eecs.umich.edu bool 1045132Sgblack@eecs.umich.edu instReady() 1055132Sgblack@eecs.umich.edu { 1065132Sgblack@eecs.umich.edu return instDone; 1075132Sgblack@eecs.umich.edu } 1085132Sgblack@eecs.umich.edu protected: 1095132Sgblack@eecs.umich.edu /// A cache of decoded instruction objects. 1105132Sgblack@eecs.umich.edu static GenericISA::BasicDecodeCache defaultCache; 1115132Sgblack@eecs.umich.edu 112 public: 113 StaticInstPtr decodeInst(ExtMachInst mach_inst); 114 115 /// Decode a machine instruction. 116 /// @param mach_inst The binary instruction to decode. 117 /// @retval A pointer to the corresponding StaticInst object. 118 StaticInstPtr 119 decode(ExtMachInst mach_inst, Addr addr) 120 { 121 return defaultCache.decode(this, mach_inst, addr); 122 } 123 124 StaticInstPtr 125 decode(PowerISA::PCState &nextPC) 126 { 127 if (!instDone) 128 return NULL; 129 instDone = false; 130 return decode(emi, nextPC.instAddr()); 131 } 132}; 133 134} // namespace PowerISA 135 136#endif // __ARCH_POWER_DECODER_HH__ 137