decoder.hh revision 9023:e9201a7bce59
18914Sandreas.hansson@arm.com/* 28914Sandreas.hansson@arm.com * Copyright (c) 2012 Google 38914Sandreas.hansson@arm.com * All rights reserved. 48914Sandreas.hansson@arm.com * 58914Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68914Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78914Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88914Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98914Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108914Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118914Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128914Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138914Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 148914Sandreas.hansson@arm.com * this software without specific prior written permission. 158914Sandreas.hansson@arm.com * 168914Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178914Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188914Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198914Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208914Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218914Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228914Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238914Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248914Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258914Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268914Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278914Sandreas.hansson@arm.com * 288914Sandreas.hansson@arm.com * Authors: Gabe Black 298914Sandreas.hansson@arm.com */ 308914Sandreas.hansson@arm.com 318914Sandreas.hansson@arm.com#ifndef __ARCH_POWER_DECODER_HH__ 328914Sandreas.hansson@arm.com#define __ARCH_POWER_DECODER_HH__ 338914Sandreas.hansson@arm.com 348914Sandreas.hansson@arm.com#include "arch/types.hh" 358914Sandreas.hansson@arm.com#include "cpu/decode_cache.hh" 368914Sandreas.hansson@arm.com#include "cpu/static_inst_fwd.hh" 378914Sandreas.hansson@arm.com 388914Sandreas.hansson@arm.comnamespace PowerISA 398914Sandreas.hansson@arm.com{ 408914Sandreas.hansson@arm.com 418914Sandreas.hansson@arm.comclass Decoder 428914Sandreas.hansson@arm.com{ 438914Sandreas.hansson@arm.com protected: 448914Sandreas.hansson@arm.com ThreadContext * tc; 458914Sandreas.hansson@arm.com 468914Sandreas.hansson@arm.com // The extended machine instruction being generated 478914Sandreas.hansson@arm.com ExtMachInst emi; 488914Sandreas.hansson@arm.com bool instDone; 498914Sandreas.hansson@arm.com 508914Sandreas.hansson@arm.com public: 518914Sandreas.hansson@arm.com Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) 528914Sandreas.hansson@arm.com { 538914Sandreas.hansson@arm.com } 548914Sandreas.hansson@arm.com 558914Sandreas.hansson@arm.com ThreadContext * 568914Sandreas.hansson@arm.com getTC() 578914Sandreas.hansson@arm.com { 588914Sandreas.hansson@arm.com return tc; 598922Swilliam.wang@arm.com } 608914Sandreas.hansson@arm.com 618914Sandreas.hansson@arm.com void 628914Sandreas.hansson@arm.com setTC(ThreadContext * _tc) 638914Sandreas.hansson@arm.com { 648914Sandreas.hansson@arm.com tc = _tc; 658914Sandreas.hansson@arm.com } 668914Sandreas.hansson@arm.com 678914Sandreas.hansson@arm.com void 688914Sandreas.hansson@arm.com process() 698914Sandreas.hansson@arm.com { 708914Sandreas.hansson@arm.com } 718922Swilliam.wang@arm.com 728922Swilliam.wang@arm.com void 738922Swilliam.wang@arm.com reset() 748922Swilliam.wang@arm.com { 758922Swilliam.wang@arm.com instDone = false; 768922Swilliam.wang@arm.com } 778922Swilliam.wang@arm.com 788922Swilliam.wang@arm.com // Use this to give data to the predecoder. This should be used 798922Swilliam.wang@arm.com // when there is control flow. 808922Swilliam.wang@arm.com void 818922Swilliam.wang@arm.com moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 828922Swilliam.wang@arm.com { 838922Swilliam.wang@arm.com emi = inst; 848922Swilliam.wang@arm.com instDone = true; 858922Swilliam.wang@arm.com } 868922Swilliam.wang@arm.com 878922Swilliam.wang@arm.com // Use this to give data to the predecoder. This should be used 888922Swilliam.wang@arm.com // when instructions are executed in order. 898922Swilliam.wang@arm.com void 908922Swilliam.wang@arm.com moreBytes(MachInst machInst) 918922Swilliam.wang@arm.com { 928922Swilliam.wang@arm.com moreBytes(0, 0, machInst); 938922Swilliam.wang@arm.com } 948922Swilliam.wang@arm.com 958922Swilliam.wang@arm.com bool 968922Swilliam.wang@arm.com needMoreBytes() 978922Swilliam.wang@arm.com { 988922Swilliam.wang@arm.com return true; 998922Swilliam.wang@arm.com } 1008922Swilliam.wang@arm.com 1018922Swilliam.wang@arm.com bool 1028922Swilliam.wang@arm.com instReady() 1038922Swilliam.wang@arm.com { 1048922Swilliam.wang@arm.com return instDone; 1058922Swilliam.wang@arm.com } 1068922Swilliam.wang@arm.com protected: 1078922Swilliam.wang@arm.com /// A cache of decoded instruction objects. 1088922Swilliam.wang@arm.com static DecodeCache defaultCache; 1098922Swilliam.wang@arm.com 1108922Swilliam.wang@arm.com public: 1118914Sandreas.hansson@arm.com StaticInstPtr decodeInst(ExtMachInst mach_inst); 1128914Sandreas.hansson@arm.com 1138914Sandreas.hansson@arm.com /// Decode a machine instruction. 1148914Sandreas.hansson@arm.com /// @param mach_inst The binary instruction to decode. 1158914Sandreas.hansson@arm.com /// @retval A pointer to the corresponding StaticInst object. 1168914Sandreas.hansson@arm.com StaticInstPtr 1178914Sandreas.hansson@arm.com decode(ExtMachInst mach_inst, Addr addr) 1188914Sandreas.hansson@arm.com { 1198914Sandreas.hansson@arm.com return defaultCache.decode(this, mach_inst, addr); 1208914Sandreas.hansson@arm.com } 1218922Swilliam.wang@arm.com 1228922Swilliam.wang@arm.com StaticInstPtr 1238922Swilliam.wang@arm.com decode(PowerISA::PCState &nextPC) 1248914Sandreas.hansson@arm.com { 1258914Sandreas.hansson@arm.com if (!instDone) 1268922Swilliam.wang@arm.com return NULL; 1278914Sandreas.hansson@arm.com instDone = false; 1288914Sandreas.hansson@arm.com return decode(emi, nextPC.instAddr()); 1298914Sandreas.hansson@arm.com } 1308914Sandreas.hansson@arm.com}; 1318914Sandreas.hansson@arm.com 1328914Sandreas.hansson@arm.com} // namespace PowerISA 1338914Sandreas.hansson@arm.com 1348914Sandreas.hansson@arm.com#endif // __ARCH_POWER_DECODER_HH__ 1358914Sandreas.hansson@arm.com