registers.hh revision 13556
112268Sradhika.jagtap@arm.com/*
212268Sradhika.jagtap@arm.com * Copyright (c) 2013 ARM Limited
312268Sradhika.jagtap@arm.com * All rights reserved
412268Sradhika.jagtap@arm.com *
512268Sradhika.jagtap@arm.com * The license below extends only to copyright in the software and shall
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712268Sradhika.jagtap@arm.com * property including but not limited to intellectual property relating
812268Sradhika.jagtap@arm.com * to a hardware implementation of the functionality of the software
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1312268Sradhika.jagtap@arm.com *
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1512268Sradhika.jagtap@arm.com * modification, are permitted provided that the following conditions are
1612268Sradhika.jagtap@arm.com * met: redistributions of source code must retain the above copyright
1712268Sradhika.jagtap@arm.com * notice, this list of conditions and the following disclaimer;
1812268Sradhika.jagtap@arm.com * redistributions in binary form must reproduce the above copyright
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2312268Sradhika.jagtap@arm.com * this software without specific prior written permission.
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3512268Sradhika.jagtap@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3612268Sradhika.jagtap@arm.com *
3712268Sradhika.jagtap@arm.com * Authors: Andreas Hansson
3812268Sradhika.jagtap@arm.com */
3912268Sradhika.jagtap@arm.com
4012268Sradhika.jagtap@arm.com#ifndef __ARCH_NULL_REGISTERS_HH__
4112268Sradhika.jagtap@arm.com#define __ARCH_NULL_REGISTERS_HH__
4212268Sradhika.jagtap@arm.com
4312268Sradhika.jagtap@arm.com#include "arch/generic/vec_reg.hh"
4412268Sradhika.jagtap@arm.com#include "arch/types.hh"
4512268Sradhika.jagtap@arm.com#include "base/types.hh"
4612268Sradhika.jagtap@arm.com
4712268Sradhika.jagtap@arm.comnamespace NullISA {
4812268Sradhika.jagtap@arm.com
4912268Sradhika.jagtap@arm.comtypedef RegVal IntReg;
5012268Sradhika.jagtap@arm.comtypedef RegVal FloatRegBits;
5112268Sradhika.jagtap@arm.comtypedef FloatRegVal FloatReg;
5212268Sradhika.jagtap@arm.comtypedef uint8_t CCReg;
5312268Sradhika.jagtap@arm.comtypedef RegVal MiscReg;
5412268Sradhika.jagtap@arm.comconst RegIndex ZeroReg = 0;
5512268Sradhika.jagtap@arm.com
5612268Sradhika.jagtap@arm.com// dummy typedefs since we don't have vector regs
5712268Sradhika.jagtap@arm.comconstexpr unsigned NumVecElemPerVecReg = 2;
5812268Sradhika.jagtap@arm.comusing VecElem = uint32_t;
5912268Sradhika.jagtap@arm.comusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
6012268Sradhika.jagtap@arm.comusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
6112268Sradhika.jagtap@arm.comusing VecRegContainer = VecReg::Container;
6212268Sradhika.jagtap@arm.com// This has to be one to prevent warnings that are treated as errors
6312268Sradhika.jagtap@arm.comconstexpr unsigned NumVecRegs = 1;
6412268Sradhika.jagtap@arm.com
6512268Sradhika.jagtap@arm.com}
6612268Sradhika.jagtap@arm.com
6712268Sradhika.jagtap@arm.com#endif // __ARCH_NULL_REGISTERS_HH__
6812268Sradhika.jagtap@arm.com