registers.hh revision 13556
112268Sradhika.jagtap@arm.com/* 212268Sradhika.jagtap@arm.com * Copyright (c) 2013 ARM Limited 312268Sradhika.jagtap@arm.com * All rights reserved 412268Sradhika.jagtap@arm.com * 512268Sradhika.jagtap@arm.com * The license below extends only to copyright in the software and shall 612268Sradhika.jagtap@arm.com * not be construed as granting a license to any other intellectual 712268Sradhika.jagtap@arm.com * property including but not limited to intellectual property relating 812268Sradhika.jagtap@arm.com * to a hardware implementation of the functionality of the software 912268Sradhika.jagtap@arm.com * licensed hereunder. You may use the software subject to the license 1012268Sradhika.jagtap@arm.com * terms below provided that you ensure that this notice is replicated 1112268Sradhika.jagtap@arm.com * unmodified and in its entirety in all distributions of the software, 1212268Sradhika.jagtap@arm.com * modified or unmodified, in source code or in binary form. 1312268Sradhika.jagtap@arm.com * 1412268Sradhika.jagtap@arm.com * Redistribution and use in source and binary forms, with or without 1512268Sradhika.jagtap@arm.com * modification, are permitted provided that the following conditions are 1612268Sradhika.jagtap@arm.com * met: redistributions of source code must retain the above copyright 1712268Sradhika.jagtap@arm.com * notice, this list of conditions and the following disclaimer; 1812268Sradhika.jagtap@arm.com * redistributions in binary form must reproduce the above copyright 1912268Sradhika.jagtap@arm.com * notice, this list of conditions and the following disclaimer in the 2012268Sradhika.jagtap@arm.com * documentation and/or other materials provided with the distribution; 2112268Sradhika.jagtap@arm.com * neither the name of the copyright holders nor the names of its 2212268Sradhika.jagtap@arm.com * contributors may be used to endorse or promote products derived from 2312268Sradhika.jagtap@arm.com * this software without specific prior written permission. 2412268Sradhika.jagtap@arm.com * 2512268Sradhika.jagtap@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612268Sradhika.jagtap@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712268Sradhika.jagtap@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812268Sradhika.jagtap@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912268Sradhika.jagtap@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012268Sradhika.jagtap@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112268Sradhika.jagtap@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212268Sradhika.jagtap@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312268Sradhika.jagtap@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412268Sradhika.jagtap@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512268Sradhika.jagtap@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612268Sradhika.jagtap@arm.com * 3712268Sradhika.jagtap@arm.com * Authors: Andreas Hansson 3812268Sradhika.jagtap@arm.com */ 3912268Sradhika.jagtap@arm.com 4012268Sradhika.jagtap@arm.com#ifndef __ARCH_NULL_REGISTERS_HH__ 4112268Sradhika.jagtap@arm.com#define __ARCH_NULL_REGISTERS_HH__ 4212268Sradhika.jagtap@arm.com 4312268Sradhika.jagtap@arm.com#include "arch/generic/vec_reg.hh" 4412268Sradhika.jagtap@arm.com#include "arch/types.hh" 4512268Sradhika.jagtap@arm.com#include "base/types.hh" 4612268Sradhika.jagtap@arm.com 4712268Sradhika.jagtap@arm.comnamespace NullISA { 4812268Sradhika.jagtap@arm.com 4912268Sradhika.jagtap@arm.comtypedef RegVal IntReg; 5012268Sradhika.jagtap@arm.comtypedef RegVal FloatRegBits; 5112268Sradhika.jagtap@arm.comtypedef FloatRegVal FloatReg; 5212268Sradhika.jagtap@arm.comtypedef uint8_t CCReg; 5312268Sradhika.jagtap@arm.comtypedef RegVal MiscReg; 5412268Sradhika.jagtap@arm.comconst RegIndex ZeroReg = 0; 5512268Sradhika.jagtap@arm.com 5612268Sradhika.jagtap@arm.com// dummy typedefs since we don't have vector regs 5712268Sradhika.jagtap@arm.comconstexpr unsigned NumVecElemPerVecReg = 2; 5812268Sradhika.jagtap@arm.comusing VecElem = uint32_t; 5912268Sradhika.jagtap@arm.comusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 6012268Sradhika.jagtap@arm.comusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 6112268Sradhika.jagtap@arm.comusing VecRegContainer = VecReg::Container; 6212268Sradhika.jagtap@arm.com// This has to be one to prevent warnings that are treated as errors 6312268Sradhika.jagtap@arm.comconstexpr unsigned NumVecRegs = 1; 6412268Sradhika.jagtap@arm.com 6512268Sradhika.jagtap@arm.com} 6612268Sradhika.jagtap@arm.com 6712268Sradhika.jagtap@arm.com#endif // __ARCH_NULL_REGISTERS_HH__ 6812268Sradhika.jagtap@arm.com