utility.hh revision 6383:31c067ae3331
14166Sgblack@eecs.umich.edu/* 210554Salexandru.dutu@amd.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 37087Snate@binkert.org * Copyright (c) 2007 MIPS Technologies, Inc. 47087Snate@binkert.org * All rights reserved. 57087Snate@binkert.org * 67087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 77087Snate@binkert.org * modification, are permitted provided that the following conditions are 87087Snate@binkert.org * met: redistributions of source code must retain the above copyright 97087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 107087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 117087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 127087Snate@binkert.org * documentation and/or other materials provided with the distribution; 137087Snate@binkert.org * neither the name of the copyright holders nor the names of its 147087Snate@binkert.org * contributors may be used to endorse or promote products derived from 154166Sgblack@eecs.umich.edu * this software without specific prior written permission. 164166Sgblack@eecs.umich.edu * 174166Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 184166Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 194166Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 204166Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 214166Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 224166Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 234166Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 244166Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 254166Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 264166Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 274166Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284166Sgblack@eecs.umich.edu * 294166Sgblack@eecs.umich.edu * Authors: Nathan Binkert 304166Sgblack@eecs.umich.edu * Steve Reinhardt 314166Sgblack@eecs.umich.edu * Korey Sewell 324166Sgblack@eecs.umich.edu */ 334166Sgblack@eecs.umich.edu 344166Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_UTILITY_HH__ 354166Sgblack@eecs.umich.edu#define __ARCH_MIPS_UTILITY_HH__ 364166Sgblack@eecs.umich.edu#include "config/full_system.hh" 374166Sgblack@eecs.umich.edu#include "arch/mips/types.hh" 384166Sgblack@eecs.umich.edu#include "arch/mips/isa_traits.hh" 394166Sgblack@eecs.umich.edu#include "base/misc.hh" 404166Sgblack@eecs.umich.edu#include "base/types.hh" 414166Sgblack@eecs.umich.edu#include "config/full_system.hh" 424166Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 434166Sgblack@eecs.umich.edu 444166Sgblack@eecs.umich.educlass ThreadContext; 4511793Sbrandon.potter@amd.com 4611793Sbrandon.potter@amd.comnamespace MipsISA { 4711854Sbrandon.potter@amd.com 4811854Sbrandon.potter@amd.comuint64_t getArgument(ThreadContext *tc, int number, bool fp); 4911854Sbrandon.potter@amd.com 5011793Sbrandon.potter@amd.com//////////////////////////////////////////////////////////////////////// 518229Snate@binkert.org// 528229Snate@binkert.org// Floating Point Utility Functions 5310554Salexandru.dutu@amd.com// 544166Sgblack@eecs.umich.eduuint64_t fpConvert(ConvertType cvt_type, double fp_val); 558229Snate@binkert.orgdouble roundFP(double val, int digits); 564166Sgblack@eecs.umich.edudouble truncFP(double val); 5712334Sgabeblack@google.com 585004Sgblack@eecs.umich.edubool getCondCode(uint32_t fcsr, int cc); 594166Sgblack@eecs.umich.eduuint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 608232Snate@binkert.orguint32_t genInvalidVector(uint32_t fcsr); 6110554Salexandru.dutu@amd.com 624166Sgblack@eecs.umich.edubool isNan(void *val_ptr, int size); 6312431Sgabeblack@google.combool isQnan(void *val_ptr, int size); 6411854Sbrandon.potter@amd.combool isSnan(void *val_ptr, int size); 654434Ssaidi@eecs.umich.edu 6611794Sbrandon.potter@amd.comstatic inline bool 6711800Sbrandon.potter@amd.cominUserMode(ThreadContext *tc) 684166Sgblack@eecs.umich.edu{ 694166Sgblack@eecs.umich.edu MiscReg Stat = tc->readMiscReg(MISCREG_STATUS); 704166Sgblack@eecs.umich.edu MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG); 714166Sgblack@eecs.umich.edu 724166Sgblack@eecs.umich.edu if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible 735958Sgblack@eecs.umich.edu (Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible 745958Sgblack@eecs.umich.edu (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode 755958Sgblack@eecs.umich.edu // Unable to use Status_CU0, etc directly, using bitfields & masks 765958Sgblack@eecs.umich.edu return true; 7711906SBrandon.Potter@amd.com } else { 785958Sgblack@eecs.umich.edu return false; 7911906SBrandon.Potter@amd.com } 805958Sgblack@eecs.umich.edu} 815958Sgblack@eecs.umich.edu 825958Sgblack@eecs.umich.edu// Instruction address compression hooks 8311704Santhony.gutierrez@amd.comstatic inline Addr realPCToFetchPC(const Addr &addr) { 8411704Santhony.gutierrez@amd.com return addr; 8511704Santhony.gutierrez@amd.com} 8611704Santhony.gutierrez@amd.com 875959Sgblack@eecs.umich.edustatic inline Addr fetchPCToRealPC(const Addr &addr) { 885959Sgblack@eecs.umich.edu return addr; 895959Sgblack@eecs.umich.edu} 905959Sgblack@eecs.umich.edu 915959Sgblack@eecs.umich.edu// the size of "fetched" instructions (not necessarily the size 925959Sgblack@eecs.umich.edu// of real instructions for PISA) 9311385Sbrandon.potter@amd.comstatic inline size_t fetchInstSize() { 945959Sgblack@eecs.umich.edu return sizeof(MachInst); 9511704Santhony.gutierrez@amd.com} 9611704Santhony.gutierrez@amd.com 9711704Santhony.gutierrez@amd.com//////////////////////////////////////////////////////////////////////// 984166Sgblack@eecs.umich.edu// 9912460Sgabeblack@google.com// Register File Utility Functions 10012460Sgabeblack@google.com// 10112460Sgabeblack@google.comstatic inline MachInst makeRegisterCopy(int dest, int src) { 10212460Sgabeblack@google.com panic("makeRegisterCopy not implemented"); 10312460Sgabeblack@google.com return 0; 10412460Sgabeblack@google.com} 10512460Sgabeblack@google.com 10612460Sgabeblack@google.comtemplate <class CPU> 10712460Sgabeblack@google.comvoid zeroRegisters(CPU *cpu); 10812431Sgabeblack@google.com 10911851Sbrandon.potter@amd.com//////////////////////////////////////////////////////////////////////// 11012431Sgabeblack@google.com// 11112448Sgabeblack@google.com// Translation stuff 11212460Sgabeblack@google.com// 11312460Sgabeblack@google.cominline Addr 11412448Sgabeblack@google.comTruncPage(Addr addr) 11512448Sgabeblack@google.com{ return addr & ~(PageBytes - 1); } 11612431Sgabeblack@google.com 11712431Sgabeblack@google.cominline Addr 1184166Sgblack@eecs.umich.eduRoundPage(Addr addr) 11911886Sbrandon.potter@amd.com{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 12011886Sbrandon.potter@amd.com 12111886Sbrandon.potter@amd.com//////////////////////////////////////////////////////////////////////// 12213613Sgabeblack@google.com// 12311886Sbrandon.potter@amd.com// CPU Utility 12411886Sbrandon.potter@amd.com// 12511886Sbrandon.potter@amd.comvoid startupCPU(ThreadContext *tc, int cpuId); 12611886Sbrandon.potter@amd.com 1275956Sgblack@eecs.umich.eduvoid copyRegs(ThreadContext *src, ThreadContext *dest); 1284166Sgblack@eecs.umich.eduvoid copyMiscRegs(ThreadContext *src, ThreadContext *dest); 12911851Sbrandon.potter@amd.com 13011851Sbrandon.potter@amd.com}; 13111851Sbrandon.potter@amd.com 1325956Sgblack@eecs.umich.edu 1336709Svince@csl.cornell.edu#endif 1346709Svince@csl.cornell.edu