utility.hh revision 6313:95f69a436c82
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Nathan Binkert 30 * Steve Reinhardt 31 * Korey Sewell 32 */ 33 34#ifndef __ARCH_MIPS_UTILITY_HH__ 35#define __ARCH_MIPS_UTILITY_HH__ 36#include "config/full_system.hh" 37#include "arch/mips/types.hh" 38#include "arch/mips/isa_traits.hh" 39#include "base/misc.hh" 40#include "base/types.hh" 41#include "config/full_system.hh" 42#include "cpu/thread_context.hh" 43 44class ThreadContext; 45 46namespace MipsISA { 47 48 uint64_t getArgument(ThreadContext *tc, int number, bool fp); 49 50 //////////////////////////////////////////////////////////////////////// 51 // 52 // Floating Point Utility Functions 53 // 54 uint64_t fpConvert(ConvertType cvt_type, double fp_val); 55 double roundFP(double val, int digits); 56 double truncFP(double val); 57 58 bool getCondCode(uint32_t fcsr, int cc); 59 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 60 uint32_t genInvalidVector(uint32_t fcsr); 61 62 bool isNan(void *val_ptr, int size); 63 bool isQnan(void *val_ptr, int size); 64 bool isSnan(void *val_ptr, int size); 65 66 static inline bool 67 inUserMode(ThreadContext *tc) 68 { 69 MiscReg Stat = tc->readMiscReg(MipsISA::Status); 70 MiscReg Dbg = tc->readMiscReg(MipsISA::Debug); 71 72 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible 73 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible 74 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode 75 // Unable to use Status_CU0, etc directly, using bitfields & masks 76 return true; 77 } else { 78 return false; 79 } 80 } 81 82 // Instruction address compression hooks 83 static inline Addr realPCToFetchPC(const Addr &addr) { 84 return addr; 85 } 86 87 static inline Addr fetchPCToRealPC(const Addr &addr) { 88 return addr; 89 } 90 91 // the size of "fetched" instructions (not necessarily the size 92 // of real instructions for PISA) 93 static inline size_t fetchInstSize() { 94 return sizeof(MachInst); 95 } 96 97 //////////////////////////////////////////////////////////////////////// 98 // 99 // Register File Utility Functions 100 // 101 static inline MachInst makeRegisterCopy(int dest, int src) { 102 panic("makeRegisterCopy not implemented"); 103 return 0; 104 } 105 106 void copyRegs(ThreadContext *src, ThreadContext *dest); 107 108 void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 109 110 111 template <class CPU> 112 void zeroRegisters(CPU *cpu); 113 114 //////////////////////////////////////////////////////////////////////// 115 // 116 // Translation stuff 117 // 118 inline Addr 119 TruncPage(Addr addr) 120 { return addr & ~(PageBytes - 1); } 121 122 inline Addr 123 RoundPage(Addr addr) 124 { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 125 126 //////////////////////////////////////////////////////////////////////// 127 // 128 // CPU Utility 129 // 130 void startupCPU(ThreadContext *tc, int cpuId); 131}; 132 133 134#endif 135