utility.hh revision 4661:44458219add1
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Nathan Binkert 30 * Steve Reinhardt 31 * Korey Sewell 32 */ 33 34#ifndef __ARCH_MIPS_UTILITY_HH__ 35#define __ARCH_MIPS_UTILITY_HH__ 36 37#include "arch/mips/types.hh" 38#include "arch/mips/isa_traits.hh" 39#include "base/misc.hh" 40#include "config/full_system.hh" 41//XXX This is needed for size_t. We should use something other than size_t 42//#include "kern/linux/linux.hh" 43#include "sim/host.hh" 44 45#include "cpu/thread_context.hh" 46 47class ThreadContext; 48 49namespace MipsISA { 50 51 //Floating Point Utility Functions 52 uint64_t fpConvert(ConvertType cvt_type, double fp_val); 53 double roundFP(double val, int digits); 54 double truncFP(double val); 55 56 bool getCondCode(uint32_t fcsr, int cc); 57 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 58 uint32_t genInvalidVector(uint32_t fcsr); 59 60 bool isNan(void *val_ptr, int size); 61 bool isQnan(void *val_ptr, int size); 62 bool isSnan(void *val_ptr, int size); 63 64 /** 65 * Function to insure ISA semantics about 0 registers. 66 * @param tc The thread context. 67 */ 68 template <class TC> 69 void zeroRegisters(TC *tc); 70 71 void startupCPU(ThreadContext *tc, int cpuId); 72 73 void copyRegs(ThreadContext *src, ThreadContext *dest); 74 75 // Instruction address compression hooks 76 static inline Addr realPCToFetchPC(const Addr &addr) { 77 return addr; 78 } 79 80 static inline Addr fetchPCToRealPC(const Addr &addr) { 81 return addr; 82 } 83 84 // the size of "fetched" instructions (not necessarily the size 85 // of real instructions for PISA) 86 static inline size_t fetchInstSize() { 87 return sizeof(MachInst); 88 } 89 90 static inline MachInst makeRegisterCopy(int dest, int src) { 91 panic("makeRegisterCopy not implemented"); 92 return 0; 93 } 94 95 static inline ExtMachInst 96 makeExtMI(MachInst inst, ThreadContext * xc) { 97#if FULL_SYSTEM 98 ExtMachInst ext_inst = inst; 99 if (xc->readPC() && 0x1) 100 return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32); 101 else 102 return ext_inst; 103#else 104 return ExtMachInst(inst); 105#endif 106 } 107}; 108 109 110#endif 111