utility.cc revision 5715:e8c1d4e669a7 
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#include "arch/mips/isa_traits.hh"
32#include "arch/mips/utility.hh"
33#include "config/full_system.hh"
34#include "cpu/thread_context.hh"
35#include "cpu/static_inst.hh"
36#include "sim/serialize.hh"
37#include "base/bitfield.hh"
38#include "base/misc.hh"
39
40#if FULL_SYSTEM
41#include "arch/mips/vtophys.hh"
42#include "mem/vport.hh"
43#endif
44
45
46using namespace MipsISA;
47using namespace std;
48
49namespace MipsISA {
50
51uint64_t
52getArgument(ThreadContext *tc, int number, bool fp)
53{
54#if FULL_SYSTEM
55    if (number < NumArgumentRegs) {
56        if (fp)
57            return tc->readFloatRegBits(ArgumentReg[number]);
58        else
59            return tc->readIntReg(ArgumentReg[number]);
60    } else {
61        Addr sp = tc->readIntReg(StackPointerReg);
62        VirtualPort *vp = tc->getVirtPort();
63        uint64_t arg = vp->read<uint64_t>(sp +
64                           (number-NumArgumentRegs) * sizeof(uint64_t));
65        return arg;
66    }
67#else
68    panic("getArgument() is Full system only\n");
69    M5_DUMMY_RETURN
70#endif
71}
72
73uint64_t
74fpConvert(ConvertType cvt_type, double fp_val)
75{
76
77    switch (cvt_type)
78    {
79      case SINGLE_TO_DOUBLE:
80        {
81            double sdouble_val = fp_val;
82            void  *sdouble_ptr = &sdouble_val;
83            uint64_t sdp_bits  = *(uint64_t *) sdouble_ptr;
84            return sdp_bits;
85        }
86
87      case SINGLE_TO_WORD:
88        {
89            int32_t sword_val  = (int32_t) fp_val;
90            void  *sword_ptr   = &sword_val;
91            uint64_t sword_bits= *(uint32_t *) sword_ptr;
92            return sword_bits;
93        }
94
95      case WORD_TO_SINGLE:
96        {
97            float wfloat_val   = fp_val;
98            void  *wfloat_ptr  = &wfloat_val;
99            uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
100            return wfloat_bits;
101        }
102
103      case WORD_TO_DOUBLE:
104        {
105            double wdouble_val = fp_val;
106            void  *wdouble_ptr = &wdouble_val;
107            uint64_t wdp_bits  = *(uint64_t *) wdouble_ptr;
108            return wdp_bits;
109        }
110
111      default:
112        panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
113        return 0;
114    }
115}
116
117double
118roundFP(double val, int digits)
119{
120    double digit_offset = pow(10.0,digits);
121    val = val * digit_offset;
122    val = val + 0.5;
123    val = floor(val);
124    val = val / digit_offset;
125    return val;
126}
127
128double
129truncFP(double val)
130{
131    int trunc_val = (int) val;
132    return (double) trunc_val;
133}
134
135bool
136getCondCode(uint32_t fcsr, int cc_idx)
137{
138    int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
139    bool cc_val = (fcsr >> shift) & 0x00000001;
140    return cc_val;
141}
142
143uint32_t
144genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
145{
146    int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
147
148    fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
149           cc_val << cc_idx |
150           bits(fcsr, cc_idx - 1, 0);
151
152    return fcsr;
153}
154
155uint32_t
156genInvalidVector(uint32_t fcsr_bits)
157{
158    //Set FCSR invalid in "flag" field
159    int invalid_offset = Invalid + Flag_Field;
160    fcsr_bits = fcsr_bits | (1 << invalid_offset);
161
162    //Set FCSR invalid in "cause" flag
163    int cause_offset = Invalid + Cause_Field;
164    fcsr_bits = fcsr_bits | (1 << cause_offset);
165
166    return fcsr_bits;
167}
168
169bool
170isNan(void *val_ptr, int size)
171{
172    switch (size)
173    {
174      case 32:
175        {
176            uint32_t val_bits = *(uint32_t *) val_ptr;
177            return (bits(val_bits, 30, 23) == 0xFF);
178        }
179
180      case 64:
181        {
182            uint64_t val_bits = *(uint64_t *) val_ptr;
183            return (bits(val_bits, 62, 52) == 0x7FF);
184        }
185
186      default:
187        panic("Type unsupported. Size mismatch\n");
188    }
189}
190
191
192bool
193isQnan(void *val_ptr, int size)
194{
195    switch (size)
196    {
197      case 32:
198        {
199            uint32_t val_bits = *(uint32_t *) val_ptr;
200            return (bits(val_bits, 30, 22) == 0x1FE);
201        }
202
203      case 64:
204        {
205            uint64_t val_bits = *(uint64_t *) val_ptr;
206            return (bits(val_bits, 62, 51) == 0xFFE);
207        }
208
209      default:
210        panic("Type unsupported. Size mismatch\n");
211    }
212}
213
214bool
215isSnan(void *val_ptr, int size)
216{
217    switch (size)
218    {
219      case 32:
220        {
221            uint32_t val_bits = *(uint32_t *) val_ptr;
222            return (bits(val_bits, 30, 22) == 0x1FF);
223        }
224
225      case 64:
226        {
227            uint64_t val_bits = *(uint64_t *) val_ptr;
228            return (bits(val_bits, 62, 51) == 0xFFF);
229        }
230
231      default:
232        panic("Type unsupported. Size mismatch\n");
233    }
234}
235
236void
237copyRegs(ThreadContext *src, ThreadContext *dest)
238{
239    panic("Copy Regs Not Implemented Yet\n");
240}
241
242void
243copyMiscRegs(ThreadContext *src, ThreadContext *dest)
244{
245    panic("Copy Misc. Regs Not Implemented Yet\n");
246}
247
248template <class CPU>
249void
250zeroRegisters(CPU *cpu)
251{
252    // Insure ISA semantics
253    // (no longer very clean due to the change in setIntReg() in the
254    // cpu model.  Consider changing later.)
255    cpu->thread->setIntReg(ZeroReg, 0);
256    cpu->thread->setFloatReg(ZeroReg, 0.0);
257}
258
259void
260startupCPU(ThreadContext *tc, int cpuId)
261{
262    tc->activate(0/*tc->threadId()*/);
263}
264
265} // namespace MipsISA
266