utility.cc revision 2980:eab855f06b79 
1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#include "arch/mips/regfile.hh"
32#include "arch/mips/utility.hh"
33#include "base/misc.hh"
34#include "base/bitfield.hh"
35
36using namespace MipsISA;
37
38uint64_t
39MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
40{
41
42    switch (cvt_type)
43    {
44      case SINGLE_TO_DOUBLE:
45        {
46            double sdouble_val = fp_val;
47            void  *sdouble_ptr = &sdouble_val;
48            uint64_t sdp_bits  = *(uint64_t *) sdouble_ptr;
49            return sdp_bits;
50        }
51
52      case SINGLE_TO_WORD:
53        {
54            int32_t sword_val  = (int32_t) fp_val;
55            void  *sword_ptr   = &sword_val;
56            uint64_t sword_bits= *(uint32_t *) sword_ptr;
57            return sword_bits;
58        }
59
60      case WORD_TO_SINGLE:
61        {
62            float wfloat_val   = fp_val;
63            void  *wfloat_ptr  = &wfloat_val;
64            uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
65            return wfloat_bits;
66        }
67
68      case WORD_TO_DOUBLE:
69        {
70            double wdouble_val = fp_val;
71            void  *wdouble_ptr = &wdouble_val;
72            uint64_t wdp_bits  = *(uint64_t *) wdouble_ptr;
73            return wdp_bits;
74        }
75
76      default:
77        panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
78        return 0;
79    }
80}
81
82double
83MipsISA::roundFP(double val, int digits)
84{
85    double digit_offset = pow(10.0,digits);
86    val = val * digit_offset;
87    val = val + 0.5;
88    val = floor(val);
89    val = val / digit_offset;
90    return val;
91}
92
93double
94MipsISA::truncFP(double val)
95{
96    int trunc_val = (int) val;
97    return (double) trunc_val;
98}
99
100bool
101MipsISA::getCondCode(uint32_t fcsr, int cc_idx)
102{
103    int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
104    bool cc_val = (fcsr >> shift) & 0x00000001;
105    return cc_val;
106}
107
108uint32_t
109MipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
110{
111    int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
112
113    fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
114           cc_val << cc_idx |
115           bits(fcsr, cc_idx - 1, 0);
116
117    return fcsr;
118}
119
120uint32_t
121MipsISA::genInvalidVector(uint32_t fcsr_bits)
122{
123    //Set FCSR invalid in "flag" field
124    int invalid_offset = Invalid + Flag_Field;
125    fcsr_bits = fcsr_bits | (1 << invalid_offset);
126
127    //Set FCSR invalid in "cause" flag
128    int cause_offset = Invalid + Cause_Field;
129    fcsr_bits = fcsr_bits | (1 << cause_offset);
130
131    return fcsr_bits;
132}
133
134bool
135MipsISA::isNan(void *val_ptr, int size)
136{
137    switch (size)
138    {
139      case 32:
140        {
141            uint32_t val_bits = *(uint32_t *) val_ptr;
142            return (bits(val_bits, 30, 23) == 0xFF);
143        }
144
145      case 64:
146        {
147            uint64_t val_bits = *(uint64_t *) val_ptr;
148            return (bits(val_bits, 62, 52) == 0x7FF);
149        }
150
151      default:
152        panic("Type unsupported. Size mismatch\n");
153    }
154}
155
156
157bool
158MipsISA::isQnan(void *val_ptr, int size)
159{
160    switch (size)
161    {
162      case 32:
163        {
164            uint32_t val_bits = *(uint32_t *) val_ptr;
165            return (bits(val_bits, 30, 22) == 0x1FE);
166        }
167
168      case 64:
169        {
170            uint64_t val_bits = *(uint64_t *) val_ptr;
171            return (bits(val_bits, 62, 51) == 0xFFE);
172        }
173
174      default:
175        panic("Type unsupported. Size mismatch\n");
176    }
177}
178
179bool
180MipsISA::isSnan(void *val_ptr, int size)
181{
182    switch (size)
183    {
184      case 32:
185        {
186            uint32_t val_bits = *(uint32_t *) val_ptr;
187            return (bits(val_bits, 30, 22) == 0x1FF);
188        }
189
190      case 64:
191        {
192            uint64_t val_bits = *(uint64_t *) val_ptr;
193            return (bits(val_bits, 62, 51) == 0xFFF);
194        }
195
196      default:
197        panic("Type unsupported. Size mismatch\n");
198    }
199}
200