tlb.hh revision 5222:bb733a878f85 
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jaidev Patwardhan
29 */
30
31#ifndef __ARCH_MIPS_TLB_HH__
32#define __ARCH_MIPS_TLB_HH__
33
34#include <map>
35
36#include "arch/mips/isa_traits.hh"
37#include "arch/mips/utility.hh"
38#include "arch/mips/vtophys.hh"
39#include "arch/mips/pagetable.hh"
40#include "base/statistics.hh"
41#include "mem/request.hh"
42#include "params/MipsDTB.hh"
43#include "params/MipsITB.hh"
44#include "sim/faults.hh"
45#include "sim/tlb.hh"
46#include "sim/sim_object.hh"
47
48class ThreadContext;
49
50/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
51   However, to maintain compatibility with other architectures, we'll
52   simply create an ITLB and DTLB that will point to the real TLB */
53namespace MipsISA {
54
55// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
56// We just need this to make compiler happy. Use "PTE" type for real entry.
57struct TlbEntry
58{
59    Addr _pageStart;
60    TlbEntry() {}
61    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
62
63    Addr pageStart()
64    {
65        return _pageStart;
66    }
67
68    void serialize(std::ostream &os)
69    {
70        SERIALIZE_SCALAR(_pageStart);
71    }
72
73    void unserialize(Checkpoint *cp, const std::string &section)
74    {
75        UNSERIALIZE_SCALAR(_pageStart);
76    }
77
78};
79
80class TLB : public SimObject
81{
82  protected:
83    typedef std::multimap<Addr, int> PageTable;
84    PageTable lookupTable;	// Quick lookup into page table
85
86    MipsISA::PTE *table;	// the Page Table
87    int size;			// TLB Size
88    int nlu;			// not last used entry (for replacement)
89
90    void nextnlu() { if (++nlu >= size) nlu = 0; }
91    MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
92
93    mutable Stats::Scalar<> read_hits;
94    mutable Stats::Scalar<> read_misses;
95    mutable Stats::Scalar<> read_acv;
96    mutable Stats::Scalar<> read_accesses;
97    mutable Stats::Scalar<> write_hits;
98    mutable Stats::Scalar<> write_misses;
99    mutable Stats::Scalar<> write_acv;
100    mutable Stats::Scalar<> write_accesses;
101    Stats::Formula hits;
102    Stats::Formula misses;
103    Stats::Formula invalids;
104    Stats::Formula accesses;
105
106  public:
107    typedef MipsTLBParams Params;
108    TLB(const Params *p);
109
110    int probeEntry(Addr vpn,uint8_t) const;
111    MipsISA::PTE *getEntry(unsigned) const;
112    virtual ~TLB();
113    int smallPages;
114    int getsize() const { return size; }
115
116    MipsISA::PTE &index(bool advance = true);
117    void insert(Addr vaddr, MipsISA::PTE &pte);
118    void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
119    void flushAll();
120
121    // static helper functions... really
122    static bool validVirtualAddress(Addr vaddr);
123
124    static Fault checkCacheability(RequestPtr &req);
125
126    // Checkpointing
127    void serialize(std::ostream &os);
128    void unserialize(Checkpoint *cp, const std::string &section);
129
130    void regStats();
131};
132
133class ITB : public TLB {
134  public:
135    typedef MipsTLBParams Params;
136    ITB(const Params *p);
137
138    Fault translate(RequestPtr &req, ThreadContext *tc);
139};
140
141class DTB : public TLB {
142  public:
143    typedef MipsTLBParams Params;
144    DTB(const Params *p);
145
146    Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
147};
148
149class UTB : public ITB, public DTB {
150  public:
151    typedef MipsTLBParams Params;
152    UTB(const Params *p);
153
154};
155
156}
157
158
159
160#endif // __MIPS_MEMORY_HH__
161