tlb.hh revision 7878
14997Sgblack@eecs.umich.edu/*
25268Sksewell@umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan
35222Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc.
44997Sgblack@eecs.umich.edu * All rights reserved.
54997Sgblack@eecs.umich.edu *
64997Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
74997Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
84997Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
94997Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
104997Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
114997Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
124997Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution;
134997Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its
144997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
154997Sgblack@eecs.umich.edu * this software without specific prior written permission.
164997Sgblack@eecs.umich.edu *
174997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
184997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
194997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
204997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
214997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
224997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
234997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
244997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
254997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
264997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
274997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
284997Sgblack@eecs.umich.edu *
295268Sksewell@umich.edu * Authors: Nathan Binkert
305268Sksewell@umich.edu *          Steve Reinhardt
315268Sksewell@umich.edu *          Jaidev Patwardhan
325268Sksewell@umich.edu *          Korey Sewell
334997Sgblack@eecs.umich.edu */
344997Sgblack@eecs.umich.edu
354997Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_TLB_HH__
364997Sgblack@eecs.umich.edu#define __ARCH_MIPS_TLB_HH__
374997Sgblack@eecs.umich.edu
385222Sksewell@umich.edu#include <map>
395222Sksewell@umich.edu
405222Sksewell@umich.edu#include "arch/mips/isa_traits.hh"
415222Sksewell@umich.edu#include "arch/mips/utility.hh"
425222Sksewell@umich.edu#include "arch/mips/vtophys.hh"
435222Sksewell@umich.edu#include "arch/mips/pagetable.hh"
445222Sksewell@umich.edu#include "base/statistics.hh"
455222Sksewell@umich.edu#include "mem/request.hh"
466022Sgblack@eecs.umich.edu#include "params/MipsTLB.hh"
477878Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh"
484997Sgblack@eecs.umich.edu#include "sim/tlb.hh"
495222Sksewell@umich.edu#include "sim/sim_object.hh"
504997Sgblack@eecs.umich.edu
515222Sksewell@umich.educlass ThreadContext;
525222Sksewell@umich.edu
535222Sksewell@umich.edu/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
545222Sksewell@umich.edu   However, to maintain compatibility with other architectures, we'll
555222Sksewell@umich.edu   simply create an ITLB and DTLB that will point to the real TLB */
565222Sksewell@umich.edunamespace MipsISA {
575222Sksewell@umich.edu
585222Sksewell@umich.edu// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
595222Sksewell@umich.edustruct TlbEntry
604997Sgblack@eecs.umich.edu{
615222Sksewell@umich.edu    Addr _pageStart;
625222Sksewell@umich.edu    TlbEntry() {}
635222Sksewell@umich.edu    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
645222Sksewell@umich.edu
655222Sksewell@umich.edu    Addr pageStart()
665014Sgblack@eecs.umich.edu    {
675222Sksewell@umich.edu        return _pageStart;
685222Sksewell@umich.edu    }
695184Sgblack@eecs.umich.edu
705877Shsul@eecs.umich.edu    void
715877Shsul@eecs.umich.edu    updateVaddr(Addr new_vaddr) {}
725877Shsul@eecs.umich.edu
735222Sksewell@umich.edu    void serialize(std::ostream &os)
745222Sksewell@umich.edu    {
755222Sksewell@umich.edu        SERIALIZE_SCALAR(_pageStart);
765222Sksewell@umich.edu    }
775014Sgblack@eecs.umich.edu
785222Sksewell@umich.edu    void unserialize(Checkpoint *cp, const std::string &section)
795222Sksewell@umich.edu    {
805222Sksewell@umich.edu        UNSERIALIZE_SCALAR(_pageStart);
815222Sksewell@umich.edu    }
825014Sgblack@eecs.umich.edu
834997Sgblack@eecs.umich.edu};
844997Sgblack@eecs.umich.edu
855358Sgblack@eecs.umich.educlass TLB : public BaseTLB
865222Sksewell@umich.edu{
875222Sksewell@umich.edu  protected:
885222Sksewell@umich.edu    typedef std::multimap<Addr, int> PageTable;
895543Ssaidi@eecs.umich.edu    PageTable lookupTable;      // Quick lookup into page table
905222Sksewell@umich.edu
915543Ssaidi@eecs.umich.edu    MipsISA::PTE *table;        // the Page Table
925543Ssaidi@eecs.umich.edu    int size;                   // TLB Size
935543Ssaidi@eecs.umich.edu    int nlu;                    // not last used entry (for replacement)
945222Sksewell@umich.edu
955222Sksewell@umich.edu    void nextnlu() { if (++nlu >= size) nlu = 0; }
965222Sksewell@umich.edu    MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
975222Sksewell@umich.edu
985999Snate@binkert.org    mutable Stats::Scalar read_hits;
995999Snate@binkert.org    mutable Stats::Scalar read_misses;
1005999Snate@binkert.org    mutable Stats::Scalar read_acv;
1015999Snate@binkert.org    mutable Stats::Scalar read_accesses;
1025999Snate@binkert.org    mutable Stats::Scalar write_hits;
1035999Snate@binkert.org    mutable Stats::Scalar write_misses;
1045999Snate@binkert.org    mutable Stats::Scalar write_acv;
1055999Snate@binkert.org    mutable Stats::Scalar write_accesses;
1065222Sksewell@umich.edu    Stats::Formula hits;
1075222Sksewell@umich.edu    Stats::Formula misses;
1085222Sksewell@umich.edu    Stats::Formula accesses;
1095222Sksewell@umich.edu
1105222Sksewell@umich.edu  public:
1115222Sksewell@umich.edu    typedef MipsTLBParams Params;
1125222Sksewell@umich.edu    TLB(const Params *p);
1135222Sksewell@umich.edu
1145222Sksewell@umich.edu    int probeEntry(Addr vpn,uint8_t) const;
1155222Sksewell@umich.edu    MipsISA::PTE *getEntry(unsigned) const;
1165222Sksewell@umich.edu    virtual ~TLB();
1175222Sksewell@umich.edu    int smallPages;
1185222Sksewell@umich.edu    int getsize() const { return size; }
1195222Sksewell@umich.edu
1205222Sksewell@umich.edu    MipsISA::PTE &index(bool advance = true);
1215222Sksewell@umich.edu    void insert(Addr vaddr, MipsISA::PTE &pte);
1225222Sksewell@umich.edu    void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
1235222Sksewell@umich.edu    void flushAll();
1245358Sgblack@eecs.umich.edu    void demapPage(Addr vaddr, uint64_t asn)
1255358Sgblack@eecs.umich.edu    {
1265358Sgblack@eecs.umich.edu        panic("demapPage unimplemented.\n");
1275358Sgblack@eecs.umich.edu    }
1285222Sksewell@umich.edu
1295222Sksewell@umich.edu    // static helper functions... really
1305222Sksewell@umich.edu    static bool validVirtualAddress(Addr vaddr);
1315222Sksewell@umich.edu
1325222Sksewell@umich.edu    static Fault checkCacheability(RequestPtr &req);
1335222Sksewell@umich.edu
1345222Sksewell@umich.edu    // Checkpointing
1355222Sksewell@umich.edu    void serialize(std::ostream &os);
1365222Sksewell@umich.edu    void unserialize(Checkpoint *cp, const std::string &section);
1375222Sksewell@umich.edu
1385222Sksewell@umich.edu    void regStats();
1395222Sksewell@umich.edu
1406023Snate@binkert.org    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
1415894Sgblack@eecs.umich.edu    void translateTiming(RequestPtr req, ThreadContext *tc,
1426023Snate@binkert.org            Translation *translation, Mode mode);
1435222Sksewell@umich.edu
1446022Sgblack@eecs.umich.edu  private:
1456022Sgblack@eecs.umich.edu    Fault translateInst(RequestPtr req, ThreadContext *tc);
1466022Sgblack@eecs.umich.edu    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
1475222Sksewell@umich.edu};
1485222Sksewell@umich.edu
1495222Sksewell@umich.edu}
1505222Sksewell@umich.edu
1515222Sksewell@umich.edu
1525222Sksewell@umich.edu
1535222Sksewell@umich.edu#endif // __MIPS_MEMORY_HH__
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