tlb.hh revision 5877
14997Sgblack@eecs.umich.edu/*
25268Sksewell@umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan
35222Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc.
44997Sgblack@eecs.umich.edu * All rights reserved.
54997Sgblack@eecs.umich.edu *
64997Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
74997Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
84997Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
94997Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
104997Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
114997Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
124997Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution;
134997Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its
144997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
154997Sgblack@eecs.umich.edu * this software without specific prior written permission.
164997Sgblack@eecs.umich.edu *
174997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
184997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
194997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
204997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
214997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
224997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
234997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
244997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
254997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
264997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
274997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
284997Sgblack@eecs.umich.edu *
295268Sksewell@umich.edu * Authors: Nathan Binkert
305268Sksewell@umich.edu *          Steve Reinhardt
315268Sksewell@umich.edu *          Jaidev Patwardhan
325268Sksewell@umich.edu *          Korey Sewell
334997Sgblack@eecs.umich.edu */
344997Sgblack@eecs.umich.edu
354997Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_TLB_HH__
364997Sgblack@eecs.umich.edu#define __ARCH_MIPS_TLB_HH__
374997Sgblack@eecs.umich.edu
385222Sksewell@umich.edu#include <map>
395222Sksewell@umich.edu
405222Sksewell@umich.edu#include "arch/mips/isa_traits.hh"
415222Sksewell@umich.edu#include "arch/mips/utility.hh"
425222Sksewell@umich.edu#include "arch/mips/vtophys.hh"
435222Sksewell@umich.edu#include "arch/mips/pagetable.hh"
445222Sksewell@umich.edu#include "base/statistics.hh"
455222Sksewell@umich.edu#include "mem/request.hh"
465034Smilesck@eecs.umich.edu#include "params/MipsDTB.hh"
475034Smilesck@eecs.umich.edu#include "params/MipsITB.hh"
485222Sksewell@umich.edu#include "sim/faults.hh"
494997Sgblack@eecs.umich.edu#include "sim/tlb.hh"
505222Sksewell@umich.edu#include "sim/sim_object.hh"
514997Sgblack@eecs.umich.edu
525222Sksewell@umich.educlass ThreadContext;
535222Sksewell@umich.edu
545222Sksewell@umich.edu/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
555222Sksewell@umich.edu   However, to maintain compatibility with other architectures, we'll
565222Sksewell@umich.edu   simply create an ITLB and DTLB that will point to the real TLB */
575222Sksewell@umich.edunamespace MipsISA {
585222Sksewell@umich.edu
595222Sksewell@umich.edu// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
605222Sksewell@umich.edustruct TlbEntry
614997Sgblack@eecs.umich.edu{
625222Sksewell@umich.edu    Addr _pageStart;
635222Sksewell@umich.edu    TlbEntry() {}
645222Sksewell@umich.edu    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
655222Sksewell@umich.edu
665222Sksewell@umich.edu    Addr pageStart()
675014Sgblack@eecs.umich.edu    {
685222Sksewell@umich.edu        return _pageStart;
695222Sksewell@umich.edu    }
705184Sgblack@eecs.umich.edu
715877Shsul@eecs.umich.edu    void
725877Shsul@eecs.umich.edu    updateVaddr(Addr new_vaddr) {}
735877Shsul@eecs.umich.edu
745222Sksewell@umich.edu    void serialize(std::ostream &os)
755222Sksewell@umich.edu    {
765222Sksewell@umich.edu        SERIALIZE_SCALAR(_pageStart);
775222Sksewell@umich.edu    }
785014Sgblack@eecs.umich.edu
795222Sksewell@umich.edu    void unserialize(Checkpoint *cp, const std::string &section)
805222Sksewell@umich.edu    {
815222Sksewell@umich.edu        UNSERIALIZE_SCALAR(_pageStart);
825222Sksewell@umich.edu    }
835014Sgblack@eecs.umich.edu
844997Sgblack@eecs.umich.edu};
854997Sgblack@eecs.umich.edu
865358Sgblack@eecs.umich.educlass TLB : public BaseTLB
875222Sksewell@umich.edu{
885222Sksewell@umich.edu  protected:
895222Sksewell@umich.edu    typedef std::multimap<Addr, int> PageTable;
905543Ssaidi@eecs.umich.edu    PageTable lookupTable;      // Quick lookup into page table
915222Sksewell@umich.edu
925543Ssaidi@eecs.umich.edu    MipsISA::PTE *table;        // the Page Table
935543Ssaidi@eecs.umich.edu    int size;                   // TLB Size
945543Ssaidi@eecs.umich.edu    int nlu;                    // not last used entry (for replacement)
955222Sksewell@umich.edu
965222Sksewell@umich.edu    void nextnlu() { if (++nlu >= size) nlu = 0; }
975222Sksewell@umich.edu    MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
985222Sksewell@umich.edu
995222Sksewell@umich.edu    mutable Stats::Scalar<> read_hits;
1005222Sksewell@umich.edu    mutable Stats::Scalar<> read_misses;
1015222Sksewell@umich.edu    mutable Stats::Scalar<> read_acv;
1025222Sksewell@umich.edu    mutable Stats::Scalar<> read_accesses;
1035222Sksewell@umich.edu    mutable Stats::Scalar<> write_hits;
1045222Sksewell@umich.edu    mutable Stats::Scalar<> write_misses;
1055222Sksewell@umich.edu    mutable Stats::Scalar<> write_acv;
1065222Sksewell@umich.edu    mutable Stats::Scalar<> write_accesses;
1075222Sksewell@umich.edu    Stats::Formula hits;
1085222Sksewell@umich.edu    Stats::Formula misses;
1095222Sksewell@umich.edu    Stats::Formula invalids;
1105222Sksewell@umich.edu    Stats::Formula accesses;
1115222Sksewell@umich.edu
1125222Sksewell@umich.edu  public:
1135222Sksewell@umich.edu    typedef MipsTLBParams Params;
1145222Sksewell@umich.edu    TLB(const Params *p);
1155222Sksewell@umich.edu
1165222Sksewell@umich.edu    int probeEntry(Addr vpn,uint8_t) const;
1175222Sksewell@umich.edu    MipsISA::PTE *getEntry(unsigned) const;
1185222Sksewell@umich.edu    virtual ~TLB();
1195222Sksewell@umich.edu    int smallPages;
1205222Sksewell@umich.edu    int getsize() const { return size; }
1215222Sksewell@umich.edu
1225222Sksewell@umich.edu    MipsISA::PTE &index(bool advance = true);
1235222Sksewell@umich.edu    void insert(Addr vaddr, MipsISA::PTE &pte);
1245222Sksewell@umich.edu    void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
1255222Sksewell@umich.edu    void flushAll();
1265358Sgblack@eecs.umich.edu    void demapPage(Addr vaddr, uint64_t asn)
1275358Sgblack@eecs.umich.edu    {
1285358Sgblack@eecs.umich.edu        panic("demapPage unimplemented.\n");
1295358Sgblack@eecs.umich.edu    }
1305222Sksewell@umich.edu
1315222Sksewell@umich.edu    // static helper functions... really
1325222Sksewell@umich.edu    static bool validVirtualAddress(Addr vaddr);
1335222Sksewell@umich.edu
1345222Sksewell@umich.edu    static Fault checkCacheability(RequestPtr &req);
1355222Sksewell@umich.edu
1365222Sksewell@umich.edu    // Checkpointing
1375222Sksewell@umich.edu    void serialize(std::ostream &os);
1385222Sksewell@umich.edu    void unserialize(Checkpoint *cp, const std::string &section);
1395222Sksewell@umich.edu
1405222Sksewell@umich.edu    void regStats();
1415222Sksewell@umich.edu};
1425222Sksewell@umich.edu
1435222Sksewell@umich.educlass ITB : public TLB {
1445222Sksewell@umich.edu  public:
1455222Sksewell@umich.edu    typedef MipsTLBParams Params;
1465222Sksewell@umich.edu    ITB(const Params *p);
1475222Sksewell@umich.edu
1485222Sksewell@umich.edu    Fault translate(RequestPtr &req, ThreadContext *tc);
1495222Sksewell@umich.edu};
1505222Sksewell@umich.edu
1515222Sksewell@umich.educlass DTB : public TLB {
1525222Sksewell@umich.edu  public:
1535222Sksewell@umich.edu    typedef MipsTLBParams Params;
1545222Sksewell@umich.edu    DTB(const Params *p);
1555222Sksewell@umich.edu
1565222Sksewell@umich.edu    Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
1575222Sksewell@umich.edu};
1585222Sksewell@umich.edu
1595222Sksewell@umich.educlass UTB : public ITB, public DTB {
1605222Sksewell@umich.edu  public:
1615222Sksewell@umich.edu    typedef MipsTLBParams Params;
1625222Sksewell@umich.edu    UTB(const Params *p);
1635222Sksewell@umich.edu
1645222Sksewell@umich.edu};
1655222Sksewell@umich.edu
1665222Sksewell@umich.edu}
1675222Sksewell@umich.edu
1685222Sksewell@umich.edu
1695222Sksewell@umich.edu
1705222Sksewell@umich.edu#endif // __MIPS_MEMORY_HH__
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