tlb.hh revision 5222
14997Sgblack@eecs.umich.edu/* 25222Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 34997Sgblack@eecs.umich.edu * All rights reserved. 44997Sgblack@eecs.umich.edu * 54997Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64997Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74997Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84997Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94997Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104997Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114997Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124997Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144997Sgblack@eecs.umich.edu * this software without specific prior written permission. 154997Sgblack@eecs.umich.edu * 164997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274997Sgblack@eecs.umich.edu * 285222Sksewell@umich.edu * Authors: Jaidev Patwardhan 294997Sgblack@eecs.umich.edu */ 304997Sgblack@eecs.umich.edu 314997Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_TLB_HH__ 324997Sgblack@eecs.umich.edu#define __ARCH_MIPS_TLB_HH__ 334997Sgblack@eecs.umich.edu 345222Sksewell@umich.edu#include <map> 355222Sksewell@umich.edu 365222Sksewell@umich.edu#include "arch/mips/isa_traits.hh" 375222Sksewell@umich.edu#include "arch/mips/utility.hh" 385222Sksewell@umich.edu#include "arch/mips/vtophys.hh" 395222Sksewell@umich.edu#include "arch/mips/pagetable.hh" 405222Sksewell@umich.edu#include "base/statistics.hh" 415222Sksewell@umich.edu#include "mem/request.hh" 425034Smilesck@eecs.umich.edu#include "params/MipsDTB.hh" 435034Smilesck@eecs.umich.edu#include "params/MipsITB.hh" 445222Sksewell@umich.edu#include "sim/faults.hh" 454997Sgblack@eecs.umich.edu#include "sim/tlb.hh" 465222Sksewell@umich.edu#include "sim/sim_object.hh" 474997Sgblack@eecs.umich.edu 485222Sksewell@umich.educlass ThreadContext; 495222Sksewell@umich.edu 505222Sksewell@umich.edu/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB 515222Sksewell@umich.edu However, to maintain compatibility with other architectures, we'll 525222Sksewell@umich.edu simply create an ITLB and DTLB that will point to the real TLB */ 535222Sksewell@umich.edunamespace MipsISA { 545222Sksewell@umich.edu 555222Sksewell@umich.edu// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA 565222Sksewell@umich.edu// We just need this to make compiler happy. Use "PTE" type for real entry. 575222Sksewell@umich.edustruct TlbEntry 584997Sgblack@eecs.umich.edu{ 595222Sksewell@umich.edu Addr _pageStart; 605222Sksewell@umich.edu TlbEntry() {} 615222Sksewell@umich.edu TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {} 625222Sksewell@umich.edu 635222Sksewell@umich.edu Addr pageStart() 645014Sgblack@eecs.umich.edu { 655222Sksewell@umich.edu return _pageStart; 665222Sksewell@umich.edu } 675184Sgblack@eecs.umich.edu 685222Sksewell@umich.edu void serialize(std::ostream &os) 695222Sksewell@umich.edu { 705222Sksewell@umich.edu SERIALIZE_SCALAR(_pageStart); 715222Sksewell@umich.edu } 725014Sgblack@eecs.umich.edu 735222Sksewell@umich.edu void unserialize(Checkpoint *cp, const std::string §ion) 745222Sksewell@umich.edu { 755222Sksewell@umich.edu UNSERIALIZE_SCALAR(_pageStart); 765222Sksewell@umich.edu } 775014Sgblack@eecs.umich.edu 784997Sgblack@eecs.umich.edu}; 794997Sgblack@eecs.umich.edu 805222Sksewell@umich.educlass TLB : public SimObject 815222Sksewell@umich.edu{ 825222Sksewell@umich.edu protected: 835222Sksewell@umich.edu typedef std::multimap<Addr, int> PageTable; 845222Sksewell@umich.edu PageTable lookupTable; // Quick lookup into page table 855222Sksewell@umich.edu 865222Sksewell@umich.edu MipsISA::PTE *table; // the Page Table 875222Sksewell@umich.edu int size; // TLB Size 885222Sksewell@umich.edu int nlu; // not last used entry (for replacement) 895222Sksewell@umich.edu 905222Sksewell@umich.edu void nextnlu() { if (++nlu >= size) nlu = 0; } 915222Sksewell@umich.edu MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const; 925222Sksewell@umich.edu 935222Sksewell@umich.edu mutable Stats::Scalar<> read_hits; 945222Sksewell@umich.edu mutable Stats::Scalar<> read_misses; 955222Sksewell@umich.edu mutable Stats::Scalar<> read_acv; 965222Sksewell@umich.edu mutable Stats::Scalar<> read_accesses; 975222Sksewell@umich.edu mutable Stats::Scalar<> write_hits; 985222Sksewell@umich.edu mutable Stats::Scalar<> write_misses; 995222Sksewell@umich.edu mutable Stats::Scalar<> write_acv; 1005222Sksewell@umich.edu mutable Stats::Scalar<> write_accesses; 1015222Sksewell@umich.edu Stats::Formula hits; 1025222Sksewell@umich.edu Stats::Formula misses; 1035222Sksewell@umich.edu Stats::Formula invalids; 1045222Sksewell@umich.edu Stats::Formula accesses; 1055222Sksewell@umich.edu 1065222Sksewell@umich.edu public: 1075222Sksewell@umich.edu typedef MipsTLBParams Params; 1085222Sksewell@umich.edu TLB(const Params *p); 1095222Sksewell@umich.edu 1105222Sksewell@umich.edu int probeEntry(Addr vpn,uint8_t) const; 1115222Sksewell@umich.edu MipsISA::PTE *getEntry(unsigned) const; 1125222Sksewell@umich.edu virtual ~TLB(); 1135222Sksewell@umich.edu int smallPages; 1145222Sksewell@umich.edu int getsize() const { return size; } 1155222Sksewell@umich.edu 1165222Sksewell@umich.edu MipsISA::PTE &index(bool advance = true); 1175222Sksewell@umich.edu void insert(Addr vaddr, MipsISA::PTE &pte); 1185222Sksewell@umich.edu void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages); 1195222Sksewell@umich.edu void flushAll(); 1205222Sksewell@umich.edu 1215222Sksewell@umich.edu // static helper functions... really 1225222Sksewell@umich.edu static bool validVirtualAddress(Addr vaddr); 1235222Sksewell@umich.edu 1245222Sksewell@umich.edu static Fault checkCacheability(RequestPtr &req); 1255222Sksewell@umich.edu 1265222Sksewell@umich.edu // Checkpointing 1275222Sksewell@umich.edu void serialize(std::ostream &os); 1285222Sksewell@umich.edu void unserialize(Checkpoint *cp, const std::string §ion); 1295222Sksewell@umich.edu 1305222Sksewell@umich.edu void regStats(); 1315222Sksewell@umich.edu}; 1325222Sksewell@umich.edu 1335222Sksewell@umich.educlass ITB : public TLB { 1345222Sksewell@umich.edu public: 1355222Sksewell@umich.edu typedef MipsTLBParams Params; 1365222Sksewell@umich.edu ITB(const Params *p); 1375222Sksewell@umich.edu 1385222Sksewell@umich.edu Fault translate(RequestPtr &req, ThreadContext *tc); 1395222Sksewell@umich.edu}; 1405222Sksewell@umich.edu 1415222Sksewell@umich.educlass DTB : public TLB { 1425222Sksewell@umich.edu public: 1435222Sksewell@umich.edu typedef MipsTLBParams Params; 1445222Sksewell@umich.edu DTB(const Params *p); 1455222Sksewell@umich.edu 1465222Sksewell@umich.edu Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false); 1475222Sksewell@umich.edu}; 1485222Sksewell@umich.edu 1495222Sksewell@umich.educlass UTB : public ITB, public DTB { 1505222Sksewell@umich.edu public: 1515222Sksewell@umich.edu typedef MipsTLBParams Params; 1525222Sksewell@umich.edu UTB(const Params *p); 1535222Sksewell@umich.edu 1545222Sksewell@umich.edu}; 1555222Sksewell@umich.edu 1565222Sksewell@umich.edu} 1575222Sksewell@umich.edu 1585222Sksewell@umich.edu 1595222Sksewell@umich.edu 1605222Sksewell@umich.edu#endif // __MIPS_MEMORY_HH__ 161