registers.hh revision 6383:31c067ae3331
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 */
31
32#ifndef __ARCH_MIPS_REGISTERS_HH__
33#define __ARCH_MIPS_REGISTERS_HH__
34
35#include "arch/mips/max_inst_regs.hh"
36#include "base/misc.hh"
37#include "base/types.hh"
38
39class ThreadContext;
40
41namespace MipsISA
42{
43
44using MipsISAInst::MaxInstSrcRegs;
45using MipsISAInst::MaxInstDestRegs;
46
47// Constants Related to the number of registers
48const int NumIntArchRegs = 32;
49const int NumIntSpecialRegs = 9;
50const int NumFloatArchRegs = 32;
51const int NumFloatSpecialRegs = 5;
52
53const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
54const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
55const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
56
57const uint32_t MIPS32_QNAN = 0x7fbfffff;
58const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
59
60enum FPControlRegNums {
61   FLOATREG_FIR = NumFloatArchRegs,
62   FLOATREG_FCCR,
63   FLOATREG_FEXR,
64   FLOATREG_FENR,
65   FLOATREG_FCSR
66};
67
68enum FCSRBits {
69    Inexact = 1,
70    Underflow,
71    Overflow,
72    DivideByZero,
73    Invalid,
74    Unimplemented
75};
76
77enum FCSRFields {
78    Flag_Field = 1,
79    Enable_Field = 6,
80    Cause_Field = 11
81};
82
83enum MiscIntRegNums {
84   INTREG_LO = NumIntArchRegs,
85   INTREG_DSP_LO0 = INTREG_LO,
86   INTREG_HI,
87   INTREG_DSP_HI0 = INTREG_HI,
88   INTREG_DSP_ACX0,
89   INTREG_DSP_LO1,
90   INTREG_DSP_HI1,
91   INTREG_DSP_ACX1,
92   INTREG_DSP_LO2,
93   INTREG_DSP_HI2,
94   INTREG_DSP_ACX2,
95   INTREG_DSP_LO3,
96   INTREG_DSP_HI3,
97   INTREG_DSP_ACX3,
98   INTREG_DSP_CONTROL
99};
100
101// semantically meaningful register indices
102const int ZeroReg = 0;
103const int AssemblerReg = 1;
104const int SyscallSuccessReg = 7;
105const int FirstArgumentReg = 4;
106const int ReturnValueReg = 2;
107
108const int KernelReg0 = 26;
109const int KernelReg1 = 27;
110const int GlobalPointerReg = 28;
111const int StackPointerReg = 29;
112const int FramePointerReg = 30;
113const int ReturnAddressReg = 31;
114
115const int SyscallPseudoReturnReg = 3;
116
117//@TODO: Implementing ShadowSets needs to
118//edit this value such that:
119//TotalArchRegs = NumIntArchRegs * ShadowSets
120const int TotalArchRegs = NumIntArchRegs;
121
122// These help enumerate all the registers for dependence tracking.
123const int FP_Base_DepTag = NumIntRegs;
124const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
125
126// Enumerate names for 'Control' Registers in the CPU
127// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
128// (Register Number-Register Select) Summary of Register
129//------------------------------------------------------
130// The first set of names classify the CP0 names as Register Banks
131// for easy indexing when using the 'RD + SEL' index combination
132// in CP0 instructions.
133enum MiscRegIndex{
134    MISCREG_INDEX = 0,       //Bank 0: 0 - 3
135    MISCREG_MVP_CONTROL,
136    MISCREG_MVP_CONF0,
137    MISCREG_MVP_CONF1,
138
139    MISCREG_CP0_RANDOM = 8,      //Bank 1: 8 - 15
140    MISCREG_VPE_CONTROL,
141    MISCREG_VPE_CONF0,
142    MISCREG_VPE_CONF1,
143    MISCREG_YQMASK,
144    MISCREG_VPE_SCHEDULE,
145    MISCREG_VPE_SCHEFBACK,
146    MISCREG_VPE_OPT,
147
148    MISCREG_ENTRYLO0 = 16,   //Bank 2: 16 - 23
149    MISCREG_TC_STATUS,
150    MISCREG_TC_BIND,
151    MISCREG_TC_RESTART,
152    MISCREG_TC_HALT,
153    MISCREG_TC_CONTEXT,
154    MISCREG_TC_SCHEDULE,
155    MISCREG_TC_SCHEFBACK,
156
157    MISCREG_ENTRYLO1 = 24,   // Bank 3: 24
158
159    MISCREG_CONTEXT = 32,    // Bank 4: 32 - 33
160    MISCREG_CONTEXT_CONFIG,
161
162    MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
163    MISCREG_PAGEGRAIN = 41,
164
165    MISCREG_WIRED = 48,          //Bank 6:48-55
166    MISCREG_SRS_CONF0,
167    MISCREG_SRS_CONF1,
168    MISCREG_SRS_CONF2,
169    MISCREG_SRS_CONF3,
170    MISCREG_SRS_CONF4,
171
172    MISCREG_HWRENA = 56,         //Bank 7: 56-63
173
174    MISCREG_BADVADDR = 64,       //Bank 8: 64-71
175
176    MISCREG_COUNT = 72,          //Bank 9: 72-79
177
178    MISCREG_ENTRYHI = 80,        //Bank 10: 80-87
179
180    MISCREG_COMPARE = 88,        //Bank 11: 88-95
181
182    MISCREG_STATUS = 96,         //Bank 12: 96-103
183    MISCREG_INTCTL,
184    MISCREG_SRSCTL,
185    MISCREG_SRSMAP,
186
187    MISCREG_CAUSE = 104,         //Bank 13: 104-111
188
189    MISCREG_EPC = 112,           //Bank 14: 112-119
190
191    MISCREG_PRID = 120,          //Bank 15: 120-127,
192    MISCREG_EBASE,
193
194    MISCREG_CONFIG = 128,        //Bank 16: 128-135
195    MISCREG_CONFIG1,
196    MISCREG_CONFIG2,
197    MISCREG_CONFIG3,
198    MISCREG_CONFIG4,
199    MISCREG_CONFIG5,
200    MISCREG_CONFIG6,
201    MISCREG_CONFIG7,
202
203
204    MISCREG_LLADDR = 136,        //Bank 17: 136-143
205
206    MISCREG_WATCHLO0 = 144,      //Bank 18: 144-151
207    MISCREG_WATCHLO1,
208    MISCREG_WATCHLO2,
209    MISCREG_WATCHLO3,
210    MISCREG_WATCHLO4,
211    MISCREG_WATCHLO5,
212    MISCREG_WATCHLO6,
213    MISCREG_WATCHLO7,
214
215    MISCREG_WATCHHI0 = 152,     //Bank 19: 152-159
216    MISCREG_WATCHHI1,
217    MISCREG_WATCHHI2,
218    MISCREG_WATCHHI3,
219    MISCREG_WATCHHI4,
220    MISCREG_WATCHHI5,
221    MISCREG_WATCHHI6,
222    MISCREG_WATCHHI7,
223
224    MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
225
226                       //Bank 21: 168-175
227
228                       //Bank 22: 176-183
229
230    MISCREG_DEBUG = 184,       //Bank 23: 184-191
231    MISCREG_TRACE_CONTROL1,
232    MISCREG_TRACE_CONTROL2,
233    MISCREG_USER_TRACE_DATA,
234    MISCREG_TRACE_BPC,
235
236    MISCREG_DEPC = 192,        //Bank 24: 192-199
237
238    MISCREG_PERFCNT0 = 200,    //Bank 25: 200-207
239    MISCREG_PERFCNT1,
240    MISCREG_PERFCNT2,
241    MISCREG_PERFCNT3,
242    MISCREG_PERFCNT4,
243    MISCREG_PERFCNT5,
244    MISCREG_PERFCNT6,
245    MISCREG_PERFCNT7,
246
247    MISCREG_ERRCTL = 208,      //Bank 26: 208-215
248
249    MISCREG_CACHEERR0 = 216,   //Bank 27: 216-223
250    MISCREG_CACHEERR1,
251    MISCREG_CACHEERR2,
252    MISCREG_CACHEERR3,
253
254    MISCREG_TAGLO0 = 224,      //Bank 28: 224-231
255    MISCREG_DATALO1,
256    MISCREG_TAGLO2,
257    MISCREG_DATALO3,
258    MISCREG_TAGLO4,
259    MISCREG_DATALO5,
260    MISCREG_TAGLO6,
261    MISCREG_DATALO7,
262
263    MISCREG_TAGHI0 = 232,      //Bank 29: 232-239
264    MISCREG_DATAHI1,
265    MISCREG_TAGHI2,
266    MISCREG_DATAHI3,
267    MISCREG_TAGHI4,
268    MISCREG_DATAHI5,
269    MISCREG_TAGHI6,
270    MISCREG_DATAHI7,
271
272
273    MISCREG_ERROR_EPC = 240,    //Bank 30: 240-247
274
275    MISCREG_DESAVE = 248,       //Bank 31: 248-256
276
277    MISCREG_LLFLAG = 257,
278
279    MISCREG_NUMREGS
280};
281
282const int TotalDataRegs = NumIntRegs + NumFloatRegs;
283
284const int NumMiscRegs = MISCREG_NUMREGS;
285
286const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
287
288typedef uint16_t  RegIndex;
289
290typedef uint32_t IntReg;
291
292// floating point register file entry type
293typedef uint32_t FloatRegBits;
294typedef float FloatReg;
295
296// cop-0/cop-1 system control register
297typedef uint64_t MiscReg;
298
299typedef union {
300    IntReg   intreg;
301    FloatReg fpreg;
302    MiscReg  ctrlreg;
303} AnyReg;
304
305} // namespace MipsISA
306
307#endif
308