registers.hh revision 13611:c8b7847b4171 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 */
31
32#ifndef __ARCH_MIPS_REGISTERS_HH__
33#define __ARCH_MIPS_REGISTERS_HH__
34
35#include "arch/generic/vec_pred_reg.hh"
36#include "arch/generic/vec_reg.hh"
37#include "arch/mips/generated/max_inst_regs.hh"
38#include "base/logging.hh"
39#include "base/types.hh"
40
41class ThreadContext;
42
43namespace MipsISA
44{
45
46using MipsISAInst::MaxInstSrcRegs;
47using MipsISAInst::MaxInstDestRegs;
48using MipsISAInst::MaxMiscDestRegs;
49
50// Constants Related to the number of registers
51const int NumIntArchRegs = 32;
52const int NumIntSpecialRegs = 9;
53const int NumFloatArchRegs = 32;
54const int NumFloatSpecialRegs = 5;
55
56const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
57const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
58const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
59const int NumVecRegs = 1;  // Not applicable to MIPS
60                           // (1 to prevent warnings)
61const int NumVecPredRegs = 1;  // Not applicable to MIPS
62                               // (1 to prevent warnings)
63const int NumCCRegs = 0;
64
65const uint32_t MIPS32_QNAN = 0x7fbfffff;
66const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
67
68enum FPControlRegNums {
69   FLOATREG_FIR = NumFloatArchRegs,
70   FLOATREG_FCCR,
71   FLOATREG_FEXR,
72   FLOATREG_FENR,
73   FLOATREG_FCSR
74};
75
76enum FCSRBits {
77    Inexact = 1,
78    Underflow,
79    Overflow,
80    DivideByZero,
81    Invalid,
82    Unimplemented
83};
84
85enum FCSRFields {
86    Flag_Field = 1,
87    Enable_Field = 6,
88    Cause_Field = 11
89};
90
91enum MiscIntRegNums {
92   INTREG_LO = NumIntArchRegs,
93   INTREG_DSP_LO0 = INTREG_LO,
94   INTREG_HI,
95   INTREG_DSP_HI0 = INTREG_HI,
96   INTREG_DSP_ACX0,
97   INTREG_DSP_LO1,
98   INTREG_DSP_HI1,
99   INTREG_DSP_ACX1,
100   INTREG_DSP_LO2,
101   INTREG_DSP_HI2,
102   INTREG_DSP_ACX2,
103   INTREG_DSP_LO3,
104   INTREG_DSP_HI3,
105   INTREG_DSP_ACX3,
106   INTREG_DSP_CONTROL
107};
108
109// semantically meaningful register indices
110const int ZeroReg = 0;
111const int AssemblerReg = 1;
112const int SyscallSuccessReg = 7;
113const int FirstArgumentReg = 4;
114const int ReturnValueReg = 2;
115
116const int KernelReg0 = 26;
117const int KernelReg1 = 27;
118const int GlobalPointerReg = 28;
119const int StackPointerReg = 29;
120const int FramePointerReg = 30;
121const int ReturnAddressReg = 31;
122
123const int SyscallPseudoReturnReg = 3;
124
125// Enumerate names for 'Control' Registers in the CPU
126// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
127// (Register Number-Register Select) Summary of Register
128//------------------------------------------------------
129// The first set of names classify the CP0 names as Register Banks
130// for easy indexing when using the 'RD + SEL' index combination
131// in CP0 instructions.
132enum MiscRegIndex{
133    MISCREG_INDEX = 0,       //Bank 0: 0 - 3
134    MISCREG_MVP_CONTROL,
135    MISCREG_MVP_CONF0,
136    MISCREG_MVP_CONF1,
137
138    MISCREG_CP0_RANDOM = 8,      //Bank 1: 8 - 15
139    MISCREG_VPE_CONTROL,
140    MISCREG_VPE_CONF0,
141    MISCREG_VPE_CONF1,
142    MISCREG_YQMASK,
143    MISCREG_VPE_SCHEDULE,
144    MISCREG_VPE_SCHEFBACK,
145    MISCREG_VPE_OPT,
146
147    MISCREG_ENTRYLO0 = 16,   //Bank 2: 16 - 23
148    MISCREG_TC_STATUS,
149    MISCREG_TC_BIND,
150    MISCREG_TC_RESTART,
151    MISCREG_TC_HALT,
152    MISCREG_TC_CONTEXT,
153    MISCREG_TC_SCHEDULE,
154    MISCREG_TC_SCHEFBACK,
155
156    MISCREG_ENTRYLO1 = 24,   // Bank 3: 24
157
158    MISCREG_CONTEXT = 32,    // Bank 4: 32 - 33
159    MISCREG_CONTEXT_CONFIG,
160
161    MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
162    MISCREG_PAGEGRAIN = 41,
163
164    MISCREG_WIRED = 48,          //Bank 6:48-55
165    MISCREG_SRS_CONF0,
166    MISCREG_SRS_CONF1,
167    MISCREG_SRS_CONF2,
168    MISCREG_SRS_CONF3,
169    MISCREG_SRS_CONF4,
170
171    MISCREG_HWRENA = 56,         //Bank 7: 56-63
172
173    MISCREG_BADVADDR = 64,       //Bank 8: 64-71
174
175    MISCREG_COUNT = 72,          //Bank 9: 72-79
176
177    MISCREG_ENTRYHI = 80,        //Bank 10: 80-87
178
179    MISCREG_COMPARE = 88,        //Bank 11: 88-95
180
181    MISCREG_STATUS = 96,         //Bank 12: 96-103
182    MISCREG_INTCTL,
183    MISCREG_SRSCTL,
184    MISCREG_SRSMAP,
185
186    MISCREG_CAUSE = 104,         //Bank 13: 104-111
187
188    MISCREG_EPC = 112,           //Bank 14: 112-119
189
190    MISCREG_PRID = 120,          //Bank 15: 120-127,
191    MISCREG_EBASE,
192
193    MISCREG_CONFIG = 128,        //Bank 16: 128-135
194    MISCREG_CONFIG1,
195    MISCREG_CONFIG2,
196    MISCREG_CONFIG3,
197    MISCREG_CONFIG4,
198    MISCREG_CONFIG5,
199    MISCREG_CONFIG6,
200    MISCREG_CONFIG7,
201
202
203    MISCREG_LLADDR = 136,        //Bank 17: 136-143
204
205    MISCREG_WATCHLO0 = 144,      //Bank 18: 144-151
206    MISCREG_WATCHLO1,
207    MISCREG_WATCHLO2,
208    MISCREG_WATCHLO3,
209    MISCREG_WATCHLO4,
210    MISCREG_WATCHLO5,
211    MISCREG_WATCHLO6,
212    MISCREG_WATCHLO7,
213
214    MISCREG_WATCHHI0 = 152,     //Bank 19: 152-159
215    MISCREG_WATCHHI1,
216    MISCREG_WATCHHI2,
217    MISCREG_WATCHHI3,
218    MISCREG_WATCHHI4,
219    MISCREG_WATCHHI5,
220    MISCREG_WATCHHI6,
221    MISCREG_WATCHHI7,
222
223    MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
224
225                       //Bank 21: 168-175
226
227                       //Bank 22: 176-183
228
229    MISCREG_DEBUG = 184,       //Bank 23: 184-191
230    MISCREG_TRACE_CONTROL1,
231    MISCREG_TRACE_CONTROL2,
232    MISCREG_USER_TRACE_DATA,
233    MISCREG_TRACE_BPC,
234
235    MISCREG_DEPC = 192,        //Bank 24: 192-199
236
237    MISCREG_PERFCNT0 = 200,    //Bank 25: 200-207
238    MISCREG_PERFCNT1,
239    MISCREG_PERFCNT2,
240    MISCREG_PERFCNT3,
241    MISCREG_PERFCNT4,
242    MISCREG_PERFCNT5,
243    MISCREG_PERFCNT6,
244    MISCREG_PERFCNT7,
245
246    MISCREG_ERRCTL = 208,      //Bank 26: 208-215
247
248    MISCREG_CACHEERR0 = 216,   //Bank 27: 216-223
249    MISCREG_CACHEERR1,
250    MISCREG_CACHEERR2,
251    MISCREG_CACHEERR3,
252
253    MISCREG_TAGLO0 = 224,      //Bank 28: 224-231
254    MISCREG_DATALO1,
255    MISCREG_TAGLO2,
256    MISCREG_DATALO3,
257    MISCREG_TAGLO4,
258    MISCREG_DATALO5,
259    MISCREG_TAGLO6,
260    MISCREG_DATALO7,
261
262    MISCREG_TAGHI0 = 232,      //Bank 29: 232-239
263    MISCREG_DATAHI1,
264    MISCREG_TAGHI2,
265    MISCREG_DATAHI3,
266    MISCREG_TAGHI4,
267    MISCREG_DATAHI5,
268    MISCREG_TAGHI6,
269    MISCREG_DATAHI7,
270
271
272    MISCREG_ERROR_EPC = 240,    //Bank 30: 240-247
273
274    MISCREG_DESAVE = 248,       //Bank 31: 248-256
275
276    MISCREG_LLFLAG = 257,
277    MISCREG_TP_VALUE,
278
279    MISCREG_NUMREGS
280};
281
282const int NumMiscRegs = MISCREG_NUMREGS;
283
284const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
285
286typedef RegVal IntReg;
287
288// floating point register file entry type
289typedef RegVal FloatReg;
290
291// cop-0/cop-1 system control register
292typedef RegVal MiscReg;
293
294// dummy typedef since we don't have CC regs
295typedef uint8_t CCReg;
296
297// Not applicable to MIPS
298using VecElem = ::DummyVecElem;
299using VecReg = ::DummyVecReg;
300using ConstVecReg = ::DummyConstVecReg;
301using VecRegContainer = ::DummyVecRegContainer;
302constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
303constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
304
305// Not applicable to MIPS
306using VecPredReg = ::DummyVecPredReg;
307using ConstVecPredReg = ::DummyConstVecPredReg;
308using VecPredRegContainer = ::DummyVecPredRegContainer;
309constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
310constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
311
312} // namespace MipsISA
313
314#endif
315