registers.hh revision 10935:acd48ddd725f
12391SN/A/* 28931Sandreas.hansson@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 38931Sandreas.hansson@arm.com * Copyright (c) 2007 MIPS Technologies, Inc. 48931Sandreas.hansson@arm.com * All rights reserved. 58931Sandreas.hansson@arm.com * 68931Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 78931Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 88931Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 98931Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 108931Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 118931Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 128931Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 132391SN/A * neither the name of the copyright holders nor the names of its 142391SN/A * contributors may be used to endorse or promote products derived from 152391SN/A * this software without specific prior written permission. 162391SN/A * 172391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282391SN/A * 292391SN/A * Authors: Korey Sewell 302391SN/A */ 312391SN/A 322391SN/A#ifndef __ARCH_MIPS_REGISTERS_HH__ 332391SN/A#define __ARCH_MIPS_REGISTERS_HH__ 342391SN/A 352391SN/A#include "arch/mips/generated/max_inst_regs.hh" 362665Ssaidi@eecs.umich.edu#include "base/misc.hh" 378931Sandreas.hansson@arm.com#include "base/types.hh" 382391SN/A 392391SN/Aclass ThreadContext; 402391SN/A 412391SN/Anamespace MipsISA 422391SN/A{ 438931Sandreas.hansson@arm.com 448931Sandreas.hansson@arm.comusing MipsISAInst::MaxInstSrcRegs; 458931Sandreas.hansson@arm.comusing MipsISAInst::MaxInstDestRegs; 464762Snate@binkert.orgusing MipsISAInst::MaxMiscDestRegs; 478931Sandreas.hansson@arm.com 488931Sandreas.hansson@arm.com// Constants Related to the number of registers 498931Sandreas.hansson@arm.comconst int NumIntArchRegs = 32; 508931Sandreas.hansson@arm.comconst int NumIntSpecialRegs = 9; 518931Sandreas.hansson@arm.comconst int NumFloatArchRegs = 32; 528931Sandreas.hansson@arm.comconst int NumFloatSpecialRegs = 5; 532391SN/A 542413SN/Aconst int MaxShadowRegSets = 16; // Maximum number of shadow register sets 552391SN/Aconst int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 562391SN/Aconst int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 578931Sandreas.hansson@arm.comconst int NumCCRegs = 0; 588931Sandreas.hansson@arm.com 593170Sstever@eecs.umich.educonst uint32_t MIPS32_QNAN = 0x7fbfffff; 608931Sandreas.hansson@arm.comconst uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); 618931Sandreas.hansson@arm.com 623170Sstever@eecs.umich.eduenum FPControlRegNums { 638931Sandreas.hansson@arm.com FLOATREG_FIR = NumFloatArchRegs, 648931Sandreas.hansson@arm.com FLOATREG_FCCR, 653170Sstever@eecs.umich.edu FLOATREG_FEXR, 668931Sandreas.hansson@arm.com FLOATREG_FENR, 678931Sandreas.hansson@arm.com FLOATREG_FCSR 683170Sstever@eecs.umich.edu}; 698931Sandreas.hansson@arm.com 708931Sandreas.hansson@arm.comenum FCSRBits { 713170Sstever@eecs.umich.edu Inexact = 1, 728931Sandreas.hansson@arm.com Underflow, 738931Sandreas.hansson@arm.com Overflow, 748719SAli.Saidi@ARM.com DivideByZero, 752391SN/A Invalid, 762391SN/A Unimplemented 778931Sandreas.hansson@arm.com}; 788931Sandreas.hansson@arm.com 798931Sandreas.hansson@arm.comenum FCSRFields { 808931Sandreas.hansson@arm.com Flag_Field = 1, 812391SN/A Enable_Field = 6, 828931Sandreas.hansson@arm.com Cause_Field = 11 838931Sandreas.hansson@arm.com}; 848931Sandreas.hansson@arm.com 858931Sandreas.hansson@arm.comenum MiscIntRegNums { 864762Snate@binkert.org INTREG_LO = NumIntArchRegs, 878931Sandreas.hansson@arm.com INTREG_DSP_LO0 = INTREG_LO, 888931Sandreas.hansson@arm.com INTREG_HI, 898931Sandreas.hansson@arm.com INTREG_DSP_HI0 = INTREG_HI, 908931Sandreas.hansson@arm.com INTREG_DSP_ACX0, 918931Sandreas.hansson@arm.com INTREG_DSP_LO1, 928931Sandreas.hansson@arm.com INTREG_DSP_HI1, 938931Sandreas.hansson@arm.com INTREG_DSP_ACX1, 948931Sandreas.hansson@arm.com INTREG_DSP_LO2, 952391SN/A INTREG_DSP_HI2, 968931Sandreas.hansson@arm.com INTREG_DSP_ACX2, 978931Sandreas.hansson@arm.com INTREG_DSP_LO3, 988931Sandreas.hansson@arm.com INTREG_DSP_HI3, 998931Sandreas.hansson@arm.com INTREG_DSP_ACX3, 1008931Sandreas.hansson@arm.com INTREG_DSP_CONTROL 1018931Sandreas.hansson@arm.com}; 1028931Sandreas.hansson@arm.com 1038923Sandreas.hansson@arm.com// semantically meaningful register indices 1048931Sandreas.hansson@arm.comconst int ZeroReg = 0; 1058931Sandreas.hansson@arm.comconst int AssemblerReg = 1; 1068931Sandreas.hansson@arm.comconst int SyscallSuccessReg = 7; 1078931Sandreas.hansson@arm.comconst int FirstArgumentReg = 4; 1088931Sandreas.hansson@arm.comconst int ReturnValueReg = 2; 1098931Sandreas.hansson@arm.com 1108923Sandreas.hansson@arm.comconst int KernelReg0 = 26; 1118931Sandreas.hansson@arm.comconst int KernelReg1 = 27; 1128931Sandreas.hansson@arm.comconst int GlobalPointerReg = 28; 1138719SAli.Saidi@ARM.comconst int StackPointerReg = 29; 1148931Sandreas.hansson@arm.comconst int FramePointerReg = 30; 1158931Sandreas.hansson@arm.comconst int ReturnAddressReg = 31; 1162391SN/A 1172391SN/Aconst int SyscallPseudoReturnReg = 3; 1188931Sandreas.hansson@arm.com 1198931Sandreas.hansson@arm.com// Enumerate names for 'Control' Registers in the CPU 1208931Sandreas.hansson@arm.com// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 1212391SN/A// (Register Number-Register Select) Summary of Register 122//------------------------------------------------------ 123// The first set of names classify the CP0 names as Register Banks 124// for easy indexing when using the 'RD + SEL' index combination 125// in CP0 instructions. 126enum MiscRegIndex{ 127 MISCREG_INDEX = 0, //Bank 0: 0 - 3 128 MISCREG_MVP_CONTROL, 129 MISCREG_MVP_CONF0, 130 MISCREG_MVP_CONF1, 131 132 MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15 133 MISCREG_VPE_CONTROL, 134 MISCREG_VPE_CONF0, 135 MISCREG_VPE_CONF1, 136 MISCREG_YQMASK, 137 MISCREG_VPE_SCHEDULE, 138 MISCREG_VPE_SCHEFBACK, 139 MISCREG_VPE_OPT, 140 141 MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23 142 MISCREG_TC_STATUS, 143 MISCREG_TC_BIND, 144 MISCREG_TC_RESTART, 145 MISCREG_TC_HALT, 146 MISCREG_TC_CONTEXT, 147 MISCREG_TC_SCHEDULE, 148 MISCREG_TC_SCHEFBACK, 149 150 MISCREG_ENTRYLO1 = 24, // Bank 3: 24 151 152 MISCREG_CONTEXT = 32, // Bank 4: 32 - 33 153 MISCREG_CONTEXT_CONFIG, 154 155 MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41 156 MISCREG_PAGEGRAIN = 41, 157 158 MISCREG_WIRED = 48, //Bank 6:48-55 159 MISCREG_SRS_CONF0, 160 MISCREG_SRS_CONF1, 161 MISCREG_SRS_CONF2, 162 MISCREG_SRS_CONF3, 163 MISCREG_SRS_CONF4, 164 165 MISCREG_HWRENA = 56, //Bank 7: 56-63 166 167 MISCREG_BADVADDR = 64, //Bank 8: 64-71 168 169 MISCREG_COUNT = 72, //Bank 9: 72-79 170 171 MISCREG_ENTRYHI = 80, //Bank 10: 80-87 172 173 MISCREG_COMPARE = 88, //Bank 11: 88-95 174 175 MISCREG_STATUS = 96, //Bank 12: 96-103 176 MISCREG_INTCTL, 177 MISCREG_SRSCTL, 178 MISCREG_SRSMAP, 179 180 MISCREG_CAUSE = 104, //Bank 13: 104-111 181 182 MISCREG_EPC = 112, //Bank 14: 112-119 183 184 MISCREG_PRID = 120, //Bank 15: 120-127, 185 MISCREG_EBASE, 186 187 MISCREG_CONFIG = 128, //Bank 16: 128-135 188 MISCREG_CONFIG1, 189 MISCREG_CONFIG2, 190 MISCREG_CONFIG3, 191 MISCREG_CONFIG4, 192 MISCREG_CONFIG5, 193 MISCREG_CONFIG6, 194 MISCREG_CONFIG7, 195 196 197 MISCREG_LLADDR = 136, //Bank 17: 136-143 198 199 MISCREG_WATCHLO0 = 144, //Bank 18: 144-151 200 MISCREG_WATCHLO1, 201 MISCREG_WATCHLO2, 202 MISCREG_WATCHLO3, 203 MISCREG_WATCHLO4, 204 MISCREG_WATCHLO5, 205 MISCREG_WATCHLO6, 206 MISCREG_WATCHLO7, 207 208 MISCREG_WATCHHI0 = 152, //Bank 19: 152-159 209 MISCREG_WATCHHI1, 210 MISCREG_WATCHHI2, 211 MISCREG_WATCHHI3, 212 MISCREG_WATCHHI4, 213 MISCREG_WATCHHI5, 214 MISCREG_WATCHHI6, 215 MISCREG_WATCHHI7, 216 217 MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167 218 219 //Bank 21: 168-175 220 221 //Bank 22: 176-183 222 223 MISCREG_DEBUG = 184, //Bank 23: 184-191 224 MISCREG_TRACE_CONTROL1, 225 MISCREG_TRACE_CONTROL2, 226 MISCREG_USER_TRACE_DATA, 227 MISCREG_TRACE_BPC, 228 229 MISCREG_DEPC = 192, //Bank 24: 192-199 230 231 MISCREG_PERFCNT0 = 200, //Bank 25: 200-207 232 MISCREG_PERFCNT1, 233 MISCREG_PERFCNT2, 234 MISCREG_PERFCNT3, 235 MISCREG_PERFCNT4, 236 MISCREG_PERFCNT5, 237 MISCREG_PERFCNT6, 238 MISCREG_PERFCNT7, 239 240 MISCREG_ERRCTL = 208, //Bank 26: 208-215 241 242 MISCREG_CACHEERR0 = 216, //Bank 27: 216-223 243 MISCREG_CACHEERR1, 244 MISCREG_CACHEERR2, 245 MISCREG_CACHEERR3, 246 247 MISCREG_TAGLO0 = 224, //Bank 28: 224-231 248 MISCREG_DATALO1, 249 MISCREG_TAGLO2, 250 MISCREG_DATALO3, 251 MISCREG_TAGLO4, 252 MISCREG_DATALO5, 253 MISCREG_TAGLO6, 254 MISCREG_DATALO7, 255 256 MISCREG_TAGHI0 = 232, //Bank 29: 232-239 257 MISCREG_DATAHI1, 258 MISCREG_TAGHI2, 259 MISCREG_DATAHI3, 260 MISCREG_TAGHI4, 261 MISCREG_DATAHI5, 262 MISCREG_TAGHI6, 263 MISCREG_DATAHI7, 264 265 266 MISCREG_ERROR_EPC = 240, //Bank 30: 240-247 267 268 MISCREG_DESAVE = 248, //Bank 31: 248-256 269 270 MISCREG_LLFLAG = 257, 271 MISCREG_TP_VALUE, 272 273 MISCREG_NUMREGS 274}; 275 276const int NumMiscRegs = MISCREG_NUMREGS; 277 278// These help enumerate all the registers for dependence tracking. 279const int FP_Reg_Base = NumIntRegs; 280const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; 281const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 282const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 283 284const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 285 286typedef uint16_t RegIndex; 287 288typedef uint32_t IntReg; 289 290// floating point register file entry type 291typedef uint32_t FloatRegBits; 292typedef float FloatReg; 293 294// cop-0/cop-1 system control register 295typedef uint64_t MiscReg; 296 297// dummy typedef since we don't have CC regs 298typedef uint8_t CCReg; 299 300typedef union { 301 IntReg intreg; 302 FloatReg fpreg; 303 MiscReg ctrlreg; 304} AnyReg; 305 306} // namespace MipsISA 307 308#endif 309