process.cc revision 11886
12567SN/A/*
27650SAli.Saidi@ARM.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
37650SAli.Saidi@ARM.com * All rights reserved.
47650SAli.Saidi@ARM.com *
57650SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without
67650SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are
77650SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright
87650SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer;
97650SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright
107650SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the
117650SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution;
127650SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its
137650SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from
142567SN/A * this software without specific prior written permission.
152567SN/A *
162567SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172567SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182567SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192567SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202567SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212567SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222567SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232567SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242567SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252567SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262567SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272567SN/A *
282567SN/A * Authors: Gabe Black
292567SN/A *          Ali Saidi
302567SN/A *          Korey Sewell
312567SN/A */
322567SN/A
332567SN/A#include "arch/mips/process.hh"
342567SN/A
352567SN/A#include "arch/mips/isa_traits.hh"
362567SN/A#include "base/loader/elf_object.hh"
372567SN/A#include "base/loader/object_file.hh"
382567SN/A#include "base/misc.hh"
392665SN/A#include "cpu/thread_context.hh"
402665SN/A#include "debug/Loader.hh"
412567SN/A#include "mem/page_table.hh"
422567SN/A#include "sim/aux_vector.hh"
436757SAli.Saidi@ARM.com#include "sim/process.hh"
446757SAli.Saidi@ARM.com#include "sim/process_impl.hh"
452567SN/A#include "sim/syscall_return.hh"
462567SN/A#include "sim/system.hh"
472567SN/A
482567SN/Ausing namespace std;
498229Snate@binkert.orgusing namespace MipsISA;
506757SAli.Saidi@ARM.com
512567SN/AMipsProcess::MipsProcess(ProcessParams * params, ObjectFile *objFile)
522567SN/A    : Process(params, objFile)
532567SN/A{
546757SAli.Saidi@ARM.com    // Set up stack. On MIPS, stack starts at the top of kuseg
552567SN/A    // user address space. MIPS stack grows down from here
568285SPrakash.Ramrakhyani@arm.com    memState->stackBase = 0x7FFFFFFF;
577650SAli.Saidi@ARM.com
587650SAli.Saidi@ARM.com    // Set pointer for next thread stack.  Reserve 8M for main stack.
597650SAli.Saidi@ARM.com    memState->nextThreadStackBase = memState->stackBase - (8 * 1024 * 1024);
607650SAli.Saidi@ARM.com
617650SAli.Saidi@ARM.com    // Set up break point (Top of Heap)
627650SAli.Saidi@ARM.com    memState->brkPoint = objFile->dataBase() + objFile->dataSize() +
638286SAli.Saidi@ARM.com                         objFile->bssSize();
648286SAli.Saidi@ARM.com    memState->brkPoint = roundUp(memState->brkPoint, PageBytes);
658286SAli.Saidi@ARM.com
668286SAli.Saidi@ARM.com    // Set up region for mmaps.  Start it 1GB above the top of the heap.
678286SAli.Saidi@ARM.com    memState->mmapEnd = memState->brkPoint + 0x40000000L;
682567SN/A}
696757SAli.Saidi@ARM.com
708286SAli.Saidi@ARM.comvoid
718286SAli.Saidi@ARM.comMipsProcess::initState()
728286SAli.Saidi@ARM.com{
738286SAli.Saidi@ARM.com    Process::initState();
748286SAli.Saidi@ARM.com
758286SAli.Saidi@ARM.com    argsInit<uint32_t>(PageBytes);
766757SAli.Saidi@ARM.com}
776757SAli.Saidi@ARM.com
788286SAli.Saidi@ARM.comtemplate<class IntType>
798286SAli.Saidi@ARM.comvoid
808286SAli.Saidi@ARM.comMipsProcess::argsInit(int pageSize)
813553SN/A{
823553SN/A    int intSize = sizeof(IntType);
837693SAli.Saidi@ARM.com
847693SAli.Saidi@ARM.com    // Patch the ld_bias for dynamic executables.
857693SAli.Saidi@ARM.com    updateBias();
867720Sgblack@eecs.umich.edu
873553SN/A    // load object file into target memory
883553SN/A    objFile->loadSections(initVirtMem);
892567SN/A
902567SN/A    typedef AuxVector<IntType> auxv_t;
912567SN/A    std::vector<auxv_t> auxv;
922567SN/A
93    ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
94    if (elfObject)
95    {
96        // Set the system page size
97        auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::PageBytes));
98        // Set the frequency at which time() increments
99        auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
100        // For statically linked executables, this is the virtual
101        // address of the program header tables if they appear in the
102        // executable image.
103        auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
104        DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
105        // This is the size of a program header entry from the elf file.
106        auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
107        // This is the number of program headers from the original elf file.
108        auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
109        // This is the base address of the ELF interpreter; it should be
110        // zero for static executables or contain the base address for
111        // dynamic executables.
112        auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
113        //The entry point to the program
114        auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
115        //Different user and group IDs
116        auxv.push_back(auxv_t(M5_AT_UID, uid()));
117        auxv.push_back(auxv_t(M5_AT_EUID, euid()));
118        auxv.push_back(auxv_t(M5_AT_GID, gid()));
119        auxv.push_back(auxv_t(M5_AT_EGID, egid()));
120    }
121
122    // Calculate how much space we need for arg & env & auxv arrays.
123    int argv_array_size = intSize * (argv.size() + 1);
124    int envp_array_size = intSize * (envp.size() + 1);
125    int auxv_array_size = intSize * 2 * (auxv.size() + 1);
126
127    int arg_data_size = 0;
128    for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
129        arg_data_size += argv[i].size() + 1;
130    }
131    int env_data_size = 0;
132    for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
133        env_data_size += envp[i].size() + 1;
134    }
135
136    int space_needed =
137        argv_array_size +
138        envp_array_size +
139        auxv_array_size +
140        arg_data_size +
141        env_data_size;
142
143    // set bottom of stack
144    memState->stackMin = memState->stackBase - space_needed;
145    // align it
146    memState->stackMin = roundDown(memState->stackMin, pageSize);
147    memState->stackSize = memState->stackBase - memState->stackMin;
148    // map memory
149    allocateMem(memState->stackMin, roundUp(memState->stackSize, pageSize));
150
151    // map out initial stack contents
152    IntType argv_array_base = memState->stackMin + intSize; // room for argc
153    IntType envp_array_base = argv_array_base + argv_array_size;
154    IntType auxv_array_base = envp_array_base + envp_array_size;
155    IntType arg_data_base = auxv_array_base + auxv_array_size;
156    IntType env_data_base = arg_data_base + arg_data_size;
157
158    // write contents to stack
159    IntType argc = argv.size();
160
161    argc = htog((IntType)argc);
162
163    initVirtMem.writeBlob(memState->stackMin, (uint8_t*)&argc, intSize);
164
165    copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
166
167    copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
168
169    // Copy the aux vector
170    for (typename vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
171        initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
172                (uint8_t*)&(auxv[x].a_type), intSize);
173        initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
174                (uint8_t*)&(auxv[x].a_val), intSize);
175    }
176
177    // Write out the terminating zeroed auxilliary vector
178    for (unsigned i = 0; i < 2; i++) {
179        const IntType zero = 0;
180        const Addr addr = auxv_array_base + 2 * intSize * (auxv.size() + i);
181        initVirtMem.writeBlob(addr, (uint8_t*)&zero, intSize);
182    }
183
184    ThreadContext *tc = system->getThreadContext(contextIds[0]);
185
186    setSyscallArg(tc, 0, argc);
187    setSyscallArg(tc, 1, argv_array_base);
188    tc->setIntReg(StackPointerReg, memState->stackMin);
189
190    tc->pcState(getStartPC());
191}
192
193
194MipsISA::IntReg
195MipsProcess::getSyscallArg(ThreadContext *tc, int &i)
196{
197    assert(i < 6);
198    return tc->readIntReg(FirstArgumentReg + i++);
199}
200
201void
202MipsProcess::setSyscallArg(ThreadContext *tc, int i, MipsISA::IntReg val)
203{
204    assert(i < 6);
205    tc->setIntReg(FirstArgumentReg + i, val);
206}
207
208void
209MipsProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
210{
211    if (sysret.successful()) {
212        // no error
213        tc->setIntReg(SyscallSuccessReg, 0);
214        tc->setIntReg(ReturnValueReg, sysret.returnValue());
215    } else {
216        // got an error, return details
217        tc->setIntReg(SyscallSuccessReg, (IntReg) -1);
218        tc->setIntReg(ReturnValueReg, sysret.errnoValue());
219    }
220}
221