pra_constants.hh revision 5222:bb733a878f85
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jaidev Patwardhan
29 */
30
31#ifndef __ARCH_MIPS_PRA_CONSTANTS_HH__
32#define __ARCH_MIPS_PRA_CONSTANTS_HH__
33
34#include "arch/mips/types.hh"
35//#include "config/full_system.hh"
36
37namespace MipsISA
38{
39  // See MIPS32(R) Architecture Reference Manual Volume - III
40  // This header file uses definitions from Revision 2.50
41
42  // Index Status Register - CP0 Reg 0, Sel 0
43
44  const unsigned Index_P_HI = 31;
45  const unsigned Index_P_LO = 31;
46  // Need to figure out how to put in the TLB specific bits here
47  // For now, we assume that the entire length is used by the index field
48  // In reality, Index_HI = N-1, where Ceiling(log2(TLB Entries))=N
49  const unsigned Index_HI = 30;
50  const unsigned Index_LO = 0;
51
52  // CP0 Reg 0, Sel 1-3 are MT registers, see mt_constants.hh
53
54  // Random Register - CP0 Reg 1, Sel 0
55  // This has a problem similar to the Index_HI fields. We'll keep both consistent at 30 for now
56  const unsigned Random_HI = 30;
57  const unsigned Random_LO = 0;
58
59  // EntryLo0 - CP0 Reg2, Sel 0  - Table 8-6, ARM Vol-3
60  const unsigned EntryLo0_Fill_HI = 31; // See Table 8-8, ARM Vol III
61  const unsigned EntryLo0_Fill_LO = 30;
62  const unsigned EntryLo0_PFN_HI  = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III)
63  const unsigned EntryLo0_PFN_LO  =  6;
64  const unsigned EntryLo0_C_HI    =  5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III)
65  const unsigned EntryLo0_C_LO    =  3;
66  const unsigned EntryLo0_D_HI    =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
67  const unsigned EntryLo0_D_LO    =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
68  const unsigned EntryLo0_V_HI    =  1; // Valid Bit
69  const unsigned EntryLo0_V_LO    =  1; // Valid Bit
70  const unsigned EntryLo0_G_HI    =  0; // Global Bit. From the ARM Vol-III, Table 8-5:
71  const unsigned EntryLo0_G_LO    =  0; // Global Bit. From the ARM Vol-III, Table 8-5:
72                                        // On a TLB write, the logical AND of the G bits from EntryLo0 and EntryLo1
73                                        // becomes the G bit in the TLB entry. If the TLB entry G bit is 1, ASID comparisons are
74                                        // ignored during TLB matches. On a read from a TLB entry, the G bits of both Lo0 and Lo1
75                                        // reflect the state of the TLB G bit.
76
77  // EntryLo1 - CP0 Reg3, Sel 0
78  const unsigned EntryLo1_G_HI       =  0;
79  const unsigned EntryLo1_G_LO       =  0;
80  const unsigned EntryLo1_V_HI       =  1; // Valid Bit
81  const unsigned EntryLo1_V_LO       =  1; // Valid Bit
82  const unsigned EntryLo1_D_HI       =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
83  const unsigned EntryLo1_D_LO       =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
84  const unsigned EntryLo1_C_HI    =  5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III)
85  const unsigned EntryLo1_C_LO    =  3;
86  const unsigned EntryLo1_PFN_HI  = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III)
87  const unsigned EntryLo1_PFN_LO  =  6;
88  const unsigned EntryLo1_Fill_LO = 30;
89  const unsigned EntryLo1_Fill_HI = 31; // See Table 8-8, ARM Vol III
90
91
92  // Context Register - CP0 Reg 4, Sel 0
93  const unsigned Context_PTEBase_HI = 31; // Used by the OS to point into current PTE array
94  const unsigned Context_PTEBase_LO = 23;
95  const unsigned Context_BadVPN2_HI = 22; // This is written by hardware on a TLB exception. Contains bits 31-13 of the
96  const unsigned Context_BadVPN2_LO = 4;  // virtual address
97  // Bits 3-0 are zeros
98
99  // PageMask Register - CP0 Reg 5, Sel 0
100  // Bits 31-29 are 0
101  const unsigned PageMask_Mask_HI = 28; // (Table 8-10, ARM Vol-III) The Mask field is a bit mask in which a "1" indicates that
102  const unsigned PageMask_Mask_LO = 13; // the corresponding bit of the virtual address should not participate in the TLB match
103  const unsigned PageMask_MaskX_HI = 12; // See Table 8-10, ARM Vol-III
104  const unsigned PageMask_MaskX_LO = 11;
105  // Bits 10-0 are zero
106
107
108  // PageGrain Register - CP0 Reg 5, Sel 1
109  const unsigned PageGrain_ASE_UP_HI = 31; // ASE specific bits (SmartMIPS)
110  const unsigned PageGrain_ASE_UP_LO = 30; //
111  const unsigned PageGrain_ELPA = 29; // Used to enable support for large physical addresses in MIPS64 processors, unused in MIPS32
112  const unsigned PageGrain_ESP = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
113  const unsigned PageGrain_ESP_HI = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
114  const unsigned PageGrain_ESP_LO = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
115  const unsigned PageGrain_ASE_DN_HI = 12;
116  const unsigned PageGrain_ASE_DN_LO = 8;
117  // Bits 27-13, 7-0 are zeros
118
119  // Wired Register - CPO Reg 6, Sel 0
120  // See note on Index register (CP0, Sel0) above
121  const unsigned Wired_HI = 30;
122  const unsigned Wired_LO = 0;
123
124
125  // HWREna Register - CP0 Reg 7, Sel 0
126  const unsigned HWREna_IMPL_HI = 31; // These bits enable access to implementation dependent hardware registers 31
127  const unsigned HWREna_IMPL_LO = 30; // and 30
128  const unsigned HWREna_Mask_HI = 3; // Each bit enables access to a particular hardware register. If bit 'n' is 1, HW Reg n is accessible
129  const unsigned HWREna_Mask_LO = 0; // See the RDHWR instruction for more details
130
131
132  // BadVAddr Register - CP0 Reg 8, Sel 0
133  const unsigned BadVAddr_HI = 31;
134  const unsigned BadVAddr_LO = 0;
135
136  // Count Register - CP0 Reg 9, Sel 0
137  const unsigned Count_HI = 31;
138  const unsigned Count_LO = 0;
139
140  // EntryHI Register - CP0 Reg 10, Sel 0
141  const unsigned EntryHi_VPN2_HI = 31;  // This field is written by hardware on a TLB exception or on a TLB read
142  const unsigned EntryHi_VPN2_LO = 13;  // and is written by software before a TLB write
143  const unsigned EntryHi_VPN2X_HI = 12; // Extension to support 1KB pages
144  const unsigned EntryHi_VPN2X_LO = 11;
145  const unsigned EntryHi_ASID_HI = 7; // Address space identifier
146  const unsigned EntryHi_ASID_LO = 0;
147
148  // Compare Register - CP0 Reg 11, Sel 0
149  const unsigned Compare_HI = 31; // Used in conjunction with Count
150  const unsigned Compare_LO = 0;
151
152  // Status Register - CP Reg 12, Sel 0
153  const unsigned Status_IE_HI = 0;
154  const unsigned Status_IE_LO = 0;
155
156  const unsigned Status_EXL = 1;
157  const unsigned Status_EXL_HI = 1;
158  const unsigned Status_EXL_LO = 1;
159  const unsigned Status_ERL_HI = 2;
160  const unsigned Status_ERL_LO = 2;
161  const unsigned Status_R0 = 3;
162  const unsigned Status_UM = 4;
163  const unsigned Status_KSU_HI = 4;  // R0 and UM are also aliased as KSU
164  const unsigned Status_KSU_LO = 3;
165  const unsigned Status_UX = 5;
166  const unsigned Status_SX = 6;
167  const unsigned Status_KX = 7;
168  const unsigned Status_IM0 = 8;
169  const unsigned Status_IM1 = 9;
170  const unsigned Status_IM2 = 10;
171  const unsigned Status_IM3 = 11;
172  const unsigned Status_IM4 = 12;
173  const unsigned Status_IM5 = 13;
174  const unsigned Status_IM6 = 14;
175  const unsigned Status_IM7 = 15;
176  const unsigned Status_IPL_HI = 15;  // IM7..IM2 are also aliased as IPL
177  const unsigned Status_IPL_LO = 10;
178  const unsigned Status_IMPL_HI = 17;
179  const unsigned Status_IMPL_LO = 16;
180  const unsigned Status_NMI = 19;
181  const unsigned Status_SR = 20;
182  const unsigned Status_TS = 21;
183  const unsigned Status_BEV = 22;
184  const unsigned Status_BEV_HI = 22;
185  const unsigned Status_BEV_LO = 22;
186  const unsigned Status_PX = 23;
187  const unsigned Status_MX = 24;
188  const unsigned Status_RE = 25;
189  const unsigned Status_FR = 26;
190  const unsigned Status_RP = 27;
191  const unsigned Status_CU3_HI = 31;
192  const unsigned Status_CU3_LO = 31;
193  const unsigned Status_CU2_HI = 30;
194  const unsigned Status_CU2_LO = 30;
195  const unsigned Status_CU1_HI = 29;
196  const unsigned Status_CU1_LO = 29;
197  const unsigned Status_CU0_HI = 28;
198  const unsigned Status_CU0_LO = 28;
199
200  // IntCtl Register - CP0 Reg 12, Sel 1
201  // Interrupt System status and control
202  const unsigned IntCtl_IPTI_HI = 31;
203  const unsigned IntCtl_IPTI_LO = 29;
204  const unsigned IntCtl_IPPCI_HI = 28;
205  const unsigned IntCtl_IPPCI_LO = 26;
206  const unsigned IntCtl_VS_HI = 9;
207  const unsigned IntCtl_VS_LO = 5;
208  // Bits 26-10, 4-0 are zeros
209
210  // SRSCtl Register - CP0 Reg 12, Sel 2
211  // Shadow Register Set Status and Control
212  const unsigned SRSCtl_HSS_HI=29; // Highest Shadow Set
213  const unsigned SRSCtl_HSS_LO=26;
214  const unsigned SRSCtl_EICSS_HI=21; //EIC interrupt mode shadow set
215  const unsigned SRSCtl_EICSS_LO=18;
216  const unsigned SRSCtl_ESS_HI=15; // Exception Shadow Set
217  const unsigned SRSCtl_ESS_LO=12;
218  const unsigned SRSCtl_PSS_HI=9; // Previous Shadow Set
219  const unsigned SRSCtl_PSS_LO=6;
220  const unsigned SRSCtl_CSS_HI=3; // Current Shadow Set
221  const unsigned SRSCtl_CSS_LO=0;
222
223  // SRSMap Register - CP0 Reg 12, Sel 3
224  // Shadow Set IPL mapping
225  const unsigned SRSMap_SSV7_HI = 31; // Shadow sets for particular vector numbers (7..0)
226  const unsigned SRSMap_SSV7_LO = 28;
227  const unsigned SRSMap_SSV6_HI = 27;
228  const unsigned SRSMap_SSV6_LO = 24;
229  const unsigned SRSMap_SSV5_HI = 23;
230  const unsigned SRSMap_SSV5_LO = 20;
231  const unsigned SRSMap_SSV4_HI = 19;
232  const unsigned SRSMap_SSV4_LO = 16;
233  const unsigned SRSMap_SSV3_HI = 15;
234  const unsigned SRSMap_SSV3_LO = 12;
235  const unsigned SRSMap_SSV2_HI = 11;
236  const unsigned SRSMap_SSV2_LO = 8;
237  const unsigned SRSMap_SSV1_HI = 7;
238  const unsigned SRSMap_SSV1_LO = 4;
239  const unsigned SRSMap_SSV0_HI = 3;
240  const unsigned SRSMap_SSV0_LO = 20;
241
242  // Cause Register - CP0 Reg 13, Sel 0
243  const unsigned Cause_BD_HI = 31;
244  const unsigned Cause_BD_LO = 31;
245  const unsigned Cause_TI_HI = 30;
246  const unsigned Cause_TI_LO = 30;
247  const unsigned Cause_CE_HI = 29;
248  const unsigned Cause_CE_LO = 28;
249  const unsigned Cause_DC = 27;
250  const unsigned Cause_PCI = 26;
251  const unsigned Cause_IV = 24;
252  const unsigned Cause_WP = 23;
253  const unsigned Cause_RIPL_HI = 15; // The individual bits of RIPL are also available as IP7..IP5
254  const unsigned Cause_RIPL_LO = 10;
255  const unsigned Cause_IP7 = 15;
256  const unsigned Cause_IP6 = 14;
257  const unsigned Cause_IP5 = 13;
258  const unsigned Cause_IP4 = 12;
259  const unsigned Cause_IP3 = 11;
260  const unsigned Cause_IP2 = 10;
261  const unsigned Cause_IP1 = 9;
262  const unsigned Cause_IP0 = 8;
263  const unsigned Cause_EXCCODE_HI = 6;
264  const unsigned Cause_EXCCODE_LO = 2;
265  // All intermediate undefined bits must be ZERO
266
267
268  // EPC Register - CP0 Reg 14, Sel 0
269  // Exception Program Counter
270  const unsigned EPC_HI = 31;
271  const unsigned EPC_LO = 0;
272
273  // PRId Register - CP0 Reg 15, Sel 0
274  // Processor Identification register
275  const unsigned PRIdCoOp_HI = 31;
276  const unsigned PRIdCoOp_LO = 24;
277  const unsigned PRIdCoID_HI = 23;
278  const unsigned PRIdCoID_LO = 16;
279  const unsigned PRIdProc_ID_HI = 15;
280  const unsigned PRIdProc_ID_LO = 8;
281  const unsigned PRIdRev_HI = 7;
282  const unsigned PRIdRev_LO = 0;
283
284
285  // EBase Register - CP0 Reg 15, Sel 1
286  // Exception Base Register
287  const unsigned EBase_MSB = 31; // MUST BE = 1
288  const unsigned EBase_EXCEPTION_Base_HI = 29;
289  const unsigned EBase_EXCEPTION_Base_LO = 12;
290  const unsigned EBase_CPUNum_HI = 9;
291  const unsigned EBase_CPUNum_LO = 0;
292  // Undefined bits must be zero
293
294  // Config Register - CP0 Reg 16, Sel 0
295  const unsigned Config_M = 31;
296  const unsigned Config_K23_HI = 30;
297  const unsigned Config_K23_LO = 28;
298  const unsigned Config_KU_HI = 27;
299  const unsigned Config_KU_LO = 25;
300  const unsigned Config_IMPL_HI = 24;
301  const unsigned Config_IMPL_LO = 16;
302  const unsigned Config_BE_HI = 15;
303  const unsigned Config_BE_LO = 15;
304  const unsigned Config_AT_HI = 14;
305  const unsigned Config_AT_LO = 13;
306  const unsigned Config_AR_HI = 12;
307  const unsigned Config_AR_LO = 10;
308  const unsigned Config_MT_HI = 9;
309  const unsigned Config_MT_LO = 7;
310  const unsigned Config_VI_HI = 3;
311  const unsigned Config_VI_LO = 3;
312  const unsigned Config_K0_HI = 2;
313  const unsigned Config_K0_LO = 0;
314
315  // Config1 Register - CP0 Reg 16, Sel 1
316  const unsigned Config1_M = 31;
317  const unsigned Config1_MMUSize_HI = 30;
318  const unsigned Config1_MMUSize_LO = 25;
319  const unsigned Config1_IS_HI = 24;
320  const unsigned Config1_IS_LO = 22;
321  const unsigned Config1_IL_HI = 21;
322  const unsigned Config1_IL_LO = 19;
323  const unsigned Config1_IA_HI = 18;
324  const unsigned Config1_IA_LO = 16;
325  const unsigned Config1_DS_HI = 15;
326  const unsigned Config1_DS_LO = 13;
327  const unsigned Config1_DL_HI = 12;
328  const unsigned Config1_DL_LO = 10;
329  const unsigned Config1_DA_HI = 9;
330  const unsigned Config1_DA_LO = 7;
331  const unsigned Config1_C2_HI = 6;
332  const unsigned Config1_C2_LO = 6;
333  const unsigned Config1_MD_HI = 5;
334  const unsigned Config1_MD_LO = 5;
335  const unsigned Config1_PC_HI = 4;
336  const unsigned Config1_PC_LO = 4;
337  const unsigned Config1_WR_HI = 3;
338  const unsigned Config1_WR_LO = 3;
339  const unsigned Config1_CA_HI = 2;
340  const unsigned Config1_CA_LO = 2;
341  const unsigned Config1_EP_HI = 1;
342  const unsigned Config1_EP_LO = 1;
343  const unsigned Config1_FP_HI = 0;
344  const unsigned Config1_FP_LO = 0;
345
346
347  // Config2 Register - CP0 Reg 16, Sel 2
348  const unsigned Config2_M = 31;
349  const unsigned Config2_TU_HI = 30;
350  const unsigned Config2_TU_LO = 28;
351  const unsigned Config2_TS_HI = 27;
352  const unsigned Config2_TS_LO = 24;
353  const unsigned Config2_TL_HI = 23;
354  const unsigned Config2_TL_LO = 20;
355  const unsigned Config2_TA_HI = 19;
356  const unsigned Config2_TA_LO = 16;
357  const unsigned Config2_SU_HI = 15;
358  const unsigned Config2_SU_LO = 12;
359  const unsigned Config2_SS_HI = 11;
360  const unsigned Config2_SS_LO = 8;
361  const unsigned Config2_SL_HI = 7;
362  const unsigned Config2_SL_LO = 4;
363  const unsigned Config2_SA_HI = 3;
364  const unsigned Config2_SA_LO = 0;
365
366  // Config3 Register - CP0 Reg 16, Sel 3
367  const unsigned Config3_M = 31;
368  const unsigned Config3_DSPP_HI = 10;
369  const unsigned Config3_DSPP_LO = 10;
370  const unsigned Config3_LPA_HI=7;
371  const unsigned Config3_LPA_LO=7;
372  const unsigned Config3_VEIC_HI=6;
373  const unsigned Config3_VEIC_LO=6;
374  const unsigned Config3_VINT_HI=5;
375  const unsigned Config3_VINT_LO=5;
376  const unsigned Config3_SP=4;
377  const unsigned Config3_SP_HI=4;
378  const unsigned Config3_SP_LO=4;
379  const unsigned Config3_MT_HI=2;
380  const unsigned Config3_MT_LO=2;
381  const unsigned Config3_SM_HI=1;
382  const unsigned Config3_SM_LO=1;
383  const unsigned Config3_TL_HI=0;
384  const unsigned Config3_TL_LO=0;
385
386
387  // LLAddr Register - CP0 Reg 17, Sel 0
388  // Load Linked Address (Physical)
389  const unsigned LLAddr_PAddr_HI = 31;
390  const unsigned LLAddr_PAddr_LO = 0;
391
392
393
394  // WatchLo Register - CP0 Reg 18, Sel 0-n
395  // See WatchHi to determine how many pairs of these registers are available
396  const unsigned WatchLo_VAddr_HI = 31;
397  const unsigned WatchLo_VAddr_LO = 3;
398  const unsigned WatchLo_I = 2;
399  const unsigned WatchLo_R = 1;
400  const unsigned WatchLo_W = 0;
401
402
403  // WatchHi Register - CP0 Reg 19, Sel 0-n
404  const unsigned WatchHi_M = 31; // If M = 1, another pair of WatchHi/Lo registers exist
405  const unsigned WatchHi_G = 30;
406  const unsigned WatchHi_ASID_HI = 23;
407  const unsigned WatchHi_ASID_LO = 16;
408  const unsigned WatchHi_Mask_HI = 11;
409  const unsigned WatchHi_Mask_LO = 3;
410  const unsigned WatchHi_I = 2;
411  const unsigned WatchHi_R = 1;
412  const unsigned WatchHi_W = 0;
413
414  // Debug Register - CP0 Reg 23, Sel 0
415
416  // TraceControl Register - CP0 Reg 23, Sel 1
417  // TraceControl2 Register - CP0 Reg 23, Sel 2
418  // UserTraceData Register - CP0 Reg 23, Sel 3
419  // TraceBPC Register - CP0 Reg 23, Sel 4
420  // DEPC Register - CP0 Reg 24, Sel 0
421
422
423  // PerfCnt Register - CP0 Reg 25, Sel 0-n
424  // Each Perf. counter that exists is mapped onto even-odd select pairs of Reg 25
425  // Even values are control registers, odd values are the actual counter
426  // The format for the control reg is:
427  const unsigned PerfCntCtl_M = 31; // Is there another pair of perf counter registers?
428  const unsigned PerfCntCtl_W = 30;
429  const unsigned PerfCntCtl_Event_HI = 10;
430  const unsigned PerfCntCtl_Event_LO = 5;
431  const unsigned PerfCntCtl_IE = 4;
432  const unsigned PerfCntCtl_U = 3;
433  const unsigned PerfCntCtl_S = 2;
434  const unsigned PerfCntCtl_K = 1;
435  const unsigned PerfCntCtl_EXL = 0;
436
437  // The format for the counter is a 32-bit value (or 64-bit for MIPS64)
438  const unsigned PerfCnt_Count_HI = 31;
439  const unsigned PerfCnt_Count_LO = 0;
440
441  // ErrCtl Register - CP0 Reg 26, Sel 0
442  // This is implementation dependent, not defined by the ISA
443
444  // CacheErr Register - CP0 Reg 27, Sel 0
445  // NOTE: Page 65 of the ARM, Volume-III indicates that there are four sel. values (0-3)
446  // used by the CacheErr registers. However, on page 134, only one sel value is shown
447  const unsigned Cache_Err_ER = 31;
448  const unsigned Cache_Err_EC = 30;
449  const unsigned Cache_Err_ED = 29;
450  const unsigned Cache_Err_ET = 28;
451  const unsigned Cache_Err_ES = 27;
452  const unsigned Cache_Err_EE = 26;
453  const unsigned Cache_Err_EB = 25;
454  const unsigned Cache_Err_IMPL_HI = 24;
455  const unsigned Cache_Err_IMPL_LO = 22;
456  const unsigned Cache_Err_Index_HI = 21;
457  const unsigned Cache_Err_Index_LO = 0;
458
459  // TagLo Register - CP0 Reg 28 - Even Selects (0,2)
460  const unsigned TagLo_PTagLo_HI = 31;
461  const unsigned TagLo_PTagLo_LO = 8;
462  const unsigned TagLo_PState_HI = 7;
463  const unsigned TagLo_PState_LO = 6;
464  const unsigned TagLo_L = 5;
465  const unsigned TagLo_IMPL_HI = 4;
466  const unsigned TagLo_IMPL_LO = 3;
467  const unsigned TagLo_P = 0;
468  // undefined bits must be written 0
469
470
471  // DataLo Register - CP0 Reg 28 - Odd Selects (1,3)
472  const unsigned DataLo_HI = 31;
473  const unsigned DataLo_LO = 0;
474
475  // TagHi Register - CP0 Reg 29 - Even Selects (0,2)
476  // Not defined by the architecture
477
478  // DataHi Register - CP0 Reg 29 - Odd Selects (1,3)
479  const unsigned DataHi_HI = 31;
480  const unsigned DataHi_LO = 0;
481
482
483  // ErrorEPC - CP0 Reg 30, Sel 0
484  const unsigned ErrorPC_HI = 31;
485  const unsigned ErrorPC_LO = 0;
486
487  // DESAVE - CP0 Reg 31, Sel 0
488
489
490
491
492
493} // namespace MipsISA
494
495#endif
496