pra_constants.hh revision 4661:44458219add1
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Jaidev Patwardhan 29 */ 30 31#ifndef __ARCH_MIPS_PRA_CONSTANTS_HH__ 32#define __ARCH_MIPS_PRA_CONSTANTS_HH__ 33 34#include "arch/mips/types.hh" 35//#include "config/full_system.hh" 36 37namespace MipsISA 38{ 39 // See MIPS32(R) Architecture Reference Manual Volume - III 40 // This header file uses definitions from Revision 2.50 41 42 // Index Status Register - CP0 Reg 0, Sel 0 43 44 const unsigned Index_P_HI = 31; 45 const unsigned Index_P_LO = 31; 46 // Need to figure out how to put in the TLB specific bits here 47 // For now, we assume that the entire length is used by the index field 48 // In reality, Index_HI = N-1, where Ceiling(log2(TLB Entries))=N 49 const unsigned Index_HI = 30; 50 const unsigned Index_LO = 0; 51 52 // CP0 Reg 0, Sel 1-3 are MT registers, see mt_constants.hh 53 54 // Random Register - CP0 Reg 1, Sel 0 55 // This has a problem similar to the Index_HI fields. We'll keep both consistent at 30 for now 56 const unsigned Random_HI = 30; 57 const unsigned Random_LO = 0; 58 59 // EntryLo0 - CP0 Reg2, Sel 0 - Table 8-6, ARM Vol-3 60 const unsigned EntryLo0_Fill_HI = 31; // See Table 8-8, ARM Vol III 61 const unsigned EntryLo0_Fill_LO = 30; 62 const unsigned EntryLo0_PFN_HI = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III) 63 const unsigned EntryLo0_PFN_LO = 6; 64 const unsigned EntryLo0_C_HI = 5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III) 65 const unsigned EntryLo0_C_LO = 3; 66 const unsigned EntryLo0_D = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 67 const unsigned EntryLo0_V = 1; // Valid Bit 68 const unsigned EntryLo0_G = 0; // Global Bit. From the ARM Vol-III, Table 8-5: 69 // On a TLB write, the logical AND of the G bits from EntryLo0 and EntryLo1 70 // becomes the G bit in the TLB entry. If the TLB entry G bit is 1, ASID comparisons are 71 // ignored during TLB matches. On a read from a TLB entry, the G bits of both Lo0 and Lo1 72 // reflect the state of the TLB G bit. 73 74 // EntryLo1 - CP0 Reg3, Sel 0 75 const unsigned EntryLo1_G = 0; 76 const unsigned EntryLo1_V = 1; // Valid Bit 77 const unsigned EntryLo1_D = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 78 const unsigned EntryLo1_C_HI = 5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III) 79 const unsigned EntryLo1_C_LO = 3; 80 const unsigned EntryLo1_PFN_HI = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III) 81 const unsigned EntryLo1_PFN_LO = 6; 82 const unsigned EntryLo1_Fill_LO = 30; 83 const unsigned EntryLo1_Fill_HI = 31; // See Table 8-8, ARM Vol III 84 85 86 // Context Register - CP0 Reg 4, Sel 0 87 const unsigned Context_PTEBase_HI = 31; // Used by the OS to point into current PTE array 88 const unsigned Context_PTEBase_LO = 23; 89 const unsigned Context_BadVPN2_HI = 22; // This is written by hardware on a TLB exception. Contains bits 31-13 of the 90 const unsigned Context_BadVPN2_LO = 4; // virtual address 91 // Bits 3-0 are zeros 92 93 // PageMask Register - CP0 Reg 5, Sel 0 94 // Bits 31-29 are 0 95 const unsigned PageMask_Mask_HI = 28; // (Table 8-10, ARM Vol-III) The Mask field is a bit mask in which a "1" indicates that 96 const unsigned PageMask_Mask_LO = 13; // the corresponding bit of the virtual address should not participate in the TLB match 97 const unsigned PageMask_MaskX_HI = 12; // See Table 8-10, ARM Vol-III 98 const unsigned PageMask_MaskX_LO = 11; 99 // Bits 10-0 are zero 100 101 102 // PageGrain Register - CP0 Reg 5, Sel 1 103 const unsigned PageGrain_ASE_UP_HI = 31; // ASE specific bits (SmartMIPS) 104 const unsigned PageGrain_ASE_UP_LO = 30; // 105 const unsigned PageGrain_ELPA = 29; // Used to enable support for large physical addresses in MIPS64 processors, unused in MIPS32 106 const unsigned PageGrain_ESP = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12 107 const unsigned PageGrain_ASE_DN_HI = 12; 108 const unsigned PageGrain_ASE_DN_LO = 8; 109 // Bits 27-13, 7-0 are zeros 110 111 // Wired Register - CPO Reg 6, Sel 0 112 // See note on Index register (CP0, Sel0) above 113 const unsigned Wired_HI = 30; 114 const unsigned Wired_LO = 0; 115 116 117 // HWREna Register - CP0 Reg 7, Sel 0 118 const unsigned HWREna_IMPL_HI = 31; // These bits enable access to implementation dependent hardware registers 31 119 const unsigned HWREna_IMPL_LO = 30; // and 30 120 const unsigned HWREna_Mask_HI = 3; // Each bit enables access to a particular hardware register. If bit 'n' is 1, HW Reg n is accessible 121 const unsigned HWREna_Mask_LO = 0; // See the RDHWR instruction for more details 122 123 124 // BadVAddr Register - CP0 Reg 8, Sel 0 125 const unsigned BadVAddr_HI = 31; 126 const unsigned BadVAddr_LO = 0; 127 128 // Count Register - CP0 Reg 9, Sel 0 129 const unsigned Count_HI = 31; 130 const unsigned Count_LO = 0; 131 132 // EntryHI Register - CP0 Reg 10, Sel 0 133 const unsigned Entry_HI_VPN2_HI = 31; // This field is written by hardware on a TLB exception or on a TLB read 134 const unsigned Entry_HI_VPN2_LO = 13; // and is written by software before a TLB write 135 const unsigned Entry_HI_VPN2X_HI = 12; // Extension to support 1KB pages 136 const unsigned Entry_HI_VPN2X_LO = 11; 137 const unsigned Entry_HI_ASID_HI = 7; // Address space identifier 138 const unsigned Entry_HI_ASID_LO = 0; 139 140 // Compare Register - CP0 Reg 11, Sel 0 141 const unsigned Compare_HI = 31; // Used in conjunction with Count 142 const unsigned Compare_LO = 0; 143 144 // Status Register - CP Reg 12, Sel 0 145 const unsigned Status_IE_HI = 0; 146 const unsigned Status_IE_LO = 0; 147 148 const unsigned Status_EXL_HI = 1; 149 const unsigned Status_EXL_LO = 1; 150 const unsigned Status_ERL_HI = 2; 151 const unsigned Status_ERL_LO = 2; 152 const unsigned Status_R0 = 3; 153 const unsigned Status_UM = 4; 154 const unsigned Status_KSU_HI = 4; // R0 and UM are also aliased as KSU 155 const unsigned Status_KSU_LO = 3; 156 const unsigned Status_UX = 5; 157 const unsigned Status_SX = 6; 158 const unsigned Status_KX = 7; 159 const unsigned Status_IM0 = 8; 160 const unsigned Status_IM1 = 9; 161 const unsigned Status_IM2 = 10; 162 const unsigned Status_IM3 = 11; 163 const unsigned Status_IM4 = 12; 164 const unsigned Status_IM5 = 13; 165 const unsigned Status_IM6 = 14; 166 const unsigned Status_IM7 = 15; 167 const unsigned Status_IPL_HI = 15; // IM7..IM2 are also aliased as IPL 168 const unsigned Status_IPL_LO = 10; 169 const unsigned Status_IMPL_HI = 17; 170 const unsigned Status_IMPL_LO = 16; 171 const unsigned Status_NMI = 19; 172 const unsigned Status_SR = 20; 173 const unsigned Status_TS = 21; 174 const unsigned Status_BEV = 22; 175 const unsigned Status_PX = 23; 176 const unsigned Status_MX = 24; 177 const unsigned Status_RE = 25; 178 const unsigned Status_FR = 26; 179 const unsigned Status_RP = 27; 180 const unsigned Status_CU3_HI = 31; 181 const unsigned Status_CU3_LO = 31; 182 const unsigned Status_CU2_HI = 30; 183 const unsigned Status_CU2_LO = 30; 184 const unsigned Status_CU1_HI = 29; 185 const unsigned Status_CU1_LO = 29; 186 const unsigned Status_CU0_HI = 28; 187 const unsigned Status_CU0_LO = 28; 188 189 // IntCtl Register - CP0 Reg 12, Sel 1 190 // Interrupt System status and control 191 const unsigned IntCtl_IPTI_HI = 31; 192 const unsigned IntCtl_IPTI_LO = 29; 193 const unsigned IntCtl_IPPCI_HI = 28; 194 const unsigned IntCtl_IPPCI_LO = 26; 195 const unsigned IntCtl_VS_HI = 9; 196 const unsigned IntCtl_VS_LO = 5; 197 // Bits 26-10, 4-0 are zeros 198 199 // SRSCtl Register - CP0 Reg 12, Sel 2 200 // Shadow Register Set Status and Control 201 const unsigned SRSCtl_HSS_HI=29; // Highest Shadow Set 202 const unsigned SRSCtl_HSS_LO=26; 203 const unsigned SRSCtl_EICSS_HI=21; //EIC interrupt mode shadow set 204 const unsigned SRSCtl_EICSS_LO=18; 205 const unsigned SRSCtl_ESS_HI=15; // Exception Shadow Set 206 const unsigned SRSCtl_ESS_LO=12; 207 const unsigned SRSCtl_PSS_HI=9; // Previous Shadow Set 208 const unsigned SRSCtl_PSS_LO=6; 209 const unsigned SRSCtl_CSS_HI=3; // Current Shadow Set 210 const unsigned SRSCtl_CSS_LO=0; 211 212 // SRSMap Register - CP0 Reg 12, Sel 3 213 // Shadow Set IPL mapping 214 const unsigned SRSMap_SSV7_HI = 31; // Shadow sets for particular vector numbers (7..0) 215 const unsigned SRSMap_SSV7_LO = 28; 216 const unsigned SRSMap_SSV6_HI = 27; 217 const unsigned SRSMap_SSV6_LO = 24; 218 const unsigned SRSMap_SSV5_HI = 23; 219 const unsigned SRSMap_SSV5_LO = 20; 220 const unsigned SRSMap_SSV4_HI = 19; 221 const unsigned SRSMap_SSV4_LO = 16; 222 const unsigned SRSMap_SSV3_HI = 15; 223 const unsigned SRSMap_SSV3_LO = 12; 224 const unsigned SRSMap_SSV2_HI = 11; 225 const unsigned SRSMap_SSV2_LO = 8; 226 const unsigned SRSMap_SSV1_HI = 7; 227 const unsigned SRSMap_SSV1_LO = 4; 228 const unsigned SRSMap_SSV0_HI = 3; 229 const unsigned SRSMap_SSV0_LO = 20; 230 231 // Cause Register - CP0 Reg 13, Sel 0 232 const unsigned Cause_BD = 31; 233 const unsigned Cause_TI = 30; 234 const unsigned Cause_CE_HI = 29; 235 const unsigned Cause_CE_LO = 28; 236 const unsigned Cause_DC = 27; 237 const unsigned Cause_PCI = 26; 238 const unsigned Cause_IV = 24; 239 const unsigned Cause_WP = 23; 240 const unsigned Cause_RIPL_HI = 15; // The individual bits of RIPL are also available as IP7..IP5 241 const unsigned Cause_RIPL_LO = 10; 242 const unsigned Cause_IP7 = 15; 243 const unsigned Cause_IP6 = 14; 244 const unsigned Cause_IP5 = 13; 245 const unsigned Cause_IP4 = 12; 246 const unsigned Cause_IP3 = 11; 247 const unsigned Cause_IP2 = 10; 248 const unsigned Cause_IP1 = 9; 249 const unsigned Cause_IP0 = 8; 250 const unsigned Cause_EXCCODE_HI = 6; 251 const unsigned Cause_EXCCODE_LO = 2; 252 // All intermediate undefined bits must be ZERO 253 254 255 // EPC Register - CP0 Reg 14, Sel 0 256 // Exception Program Counter 257 const unsigned EPC_HI = 31; 258 const unsigned EPC_LO = 0; 259 260 // PRId Register - CP0 Reg 15, Sel 0 261 // Processor Identification register 262 const unsigned PRIdCoOp_HI = 31; 263 const unsigned PRIdCoOp_LO = 24; 264 const unsigned PRIdCoID_HI = 23; 265 const unsigned PRIdCoID_LO = 16; 266 const unsigned PRIdProc_ID_HI = 15; 267 const unsigned PRIdProc_ID_LO = 8; 268 const unsigned PRIdRev_HI = 7; 269 const unsigned PRIdRev_LO = 0; 270 271 272 // EBase Register - CP0 Reg 15, Sel 1 273 // Exception Base Register 274 const unsigned EBase_MSB = 31; // MUST BE = 1 275 const unsigned EBase_EXCEPTION_Base_HI = 29; 276 const unsigned EBase_EXCEPTION_Base_LO = 12; 277 const unsigned EBase_CPUNum_HI = 9; 278 const unsigned EBase_CPUNum_LO = 0; 279 // Undefined bits must be zero 280 281 // Config Register - CP0 Reg 16, Sel 0 282 const unsigned Config_M = 31; 283 const unsigned Config_K23_HI = 30; 284 const unsigned Config_K23_LO = 28; 285 const unsigned Config_KU_HI = 27; 286 const unsigned Config_KU_LO = 25; 287 const unsigned Config_IMPL_HI = 24; 288 const unsigned Config_IMPL_LO = 16; 289 const unsigned Config_BE = 15; 290 const unsigned Config_AT_HI = 14; 291 const unsigned Config_AT_LO = 13; 292 const unsigned Config_AR_HI = 12; 293 const unsigned Config_AR_LO = 10; 294 const unsigned Config_MT_HI = 9; 295 const unsigned Config_MT_LO = 7; 296 const unsigned Config_VI = 3; 297 const unsigned Config_K0_HI = 2; 298 const unsigned Config_K0_LO = 0; 299 300 // Config1 Register - CP0 Reg 16, Sel 1 301 const unsigned Config1_M = 31; 302 const unsigned Config1_MMUSize_HI = 30; 303 const unsigned Config1_MMUSize_LO = 25; 304 const unsigned Config1_IS_HI = 24; 305 const unsigned Config1_IS_LO = 22; 306 const unsigned Config1_IL_HI = 21; 307 const unsigned Config1_IL_LO = 19; 308 const unsigned Config1_IA_HI = 18; 309 const unsigned Config1_IA_LO = 16; 310 const unsigned Config1_DS_HI = 15; 311 const unsigned Config1_DS_LO = 13; 312 const unsigned Config1_DL_HI = 12; 313 const unsigned Config1_DL_LO = 10; 314 const unsigned Config1_DA_HI = 9; 315 const unsigned Config1_DA_LO = 7; 316 const unsigned Config1_C2 = 6; 317 const unsigned Config1_MD = 5; 318 const unsigned Config1_PC = 4; 319 const unsigned Config1_WR = 3; 320 const unsigned Config1_CA = 2; 321 const unsigned Config1_EP = 1; 322 const unsigned Config1_FP = 0; 323 324 325 // Config2 Register - CP0 Reg 16, Sel 2 326 const unsigned Config2_M = 31; 327 const unsigned Config2_TU_HI = 30; 328 const unsigned Config2_TU_LO = 28; 329 const unsigned Config2_TS_HI = 27; 330 const unsigned Config2_TS_LO = 24; 331 const unsigned Config2_TL_HI = 23; 332 const unsigned Config2_TL_LO = 20; 333 const unsigned Config2_TA_HI = 19; 334 const unsigned Config2_TA_LO = 16; 335 const unsigned Config2_SU_HI = 15; 336 const unsigned Config2_SU_LO = 12; 337 const unsigned Config2_SS_HI = 11; 338 const unsigned Config2_SS_LO = 8; 339 const unsigned Config2_SL_HI = 7; 340 const unsigned Config2_SL_LO = 4; 341 const unsigned Config2_SA_HI = 3; 342 const unsigned Config2_SA_LO = 0; 343 344 // Config3 Register - CP0 Reg 16, Sel 3 345 const unsigned Config3_M = 31; 346 const unsigned Config3_DSPP = 10; 347 const unsigned Config3_LPA=7; 348 const unsigned Config3_VEIC=6; 349 const unsigned Config3_VINT=5; 350 const unsigned Config3_SP=4; 351 const unsigned Config3_MT=2; 352 const unsigned Config3_SM=1; 353 const unsigned Config3_TL=0; 354 355 356 // LLAddr Register - CP0 Reg 17, Sel 0 357 // Load Linked Address (Physical) 358 const unsigned LLAddr_PAddr_HI = 31; 359 const unsigned LLAddr_PAddr_LO = 0; 360 361 362 363 // WatchLo Register - CP0 Reg 18, Sel 0-n 364 // See WatchHi to determine how many pairs of these registers are available 365 const unsigned WatchLo_VAddr_HI = 31; 366 const unsigned WatchLo_VAddr_LO = 3; 367 const unsigned WatchLo_I = 2; 368 const unsigned WatchLo_R = 1; 369 const unsigned WatchLo_W = 0; 370 371 372 // WatchHi Register - CP0 Reg 19, Sel 0-n 373 const unsigned WatchHi_M = 31; // If M = 1, another pair of WatchHi/Lo registers exist 374 const unsigned WatchHi_G = 30; 375 const unsigned WatchHi_ASID_HI = 23; 376 const unsigned WatchHi_ASID_LO = 16; 377 const unsigned WatchHi_Mask_HI = 11; 378 const unsigned WatchHi_Mask_LO = 3; 379 const unsigned WatchHi_I = 2; 380 const unsigned WatchHi_R = 1; 381 const unsigned WatchHi_W = 0; 382 383 // Debug Register - CP0 Reg 23, Sel 0 384 385 // TraceControl Register - CP0 Reg 23, Sel 1 386 // TraceControl2 Register - CP0 Reg 23, Sel 2 387 // UserTraceData Register - CP0 Reg 23, Sel 3 388 // TraceBPC Register - CP0 Reg 23, Sel 4 389 // DEPC Register - CP0 Reg 24, Sel 0 390 391 392 // PerfCnt Register - CP0 Reg 25, Sel 0-n 393 // Each Perf. counter that exists is mapped onto even-odd select pairs of Reg 25 394 // Even values are control registers, odd values are the actual counter 395 // The format for the control reg is: 396 const unsigned PerfCntCtl_M = 31; // Is there another pair of perf counter registers? 397 const unsigned PerfCntCtl_W = 30; 398 const unsigned PerfCntCtl_Event_HI = 10; 399 const unsigned PerfCntCtl_Event_LO = 5; 400 const unsigned PerfCntCtl_IE = 4; 401 const unsigned PerfCntCtl_U = 3; 402 const unsigned PerfCntCtl_S = 2; 403 const unsigned PerfCntCtl_K = 1; 404 const unsigned PerfCntCtl_EXL = 0; 405 406 // The format for the counter is a 32-bit value (or 64-bit for MIPS64) 407 const unsigned PerfCnt_Count_HI = 31; 408 const unsigned PerfCnt_Count_LO = 0; 409 410 // ErrCtl Register - CP0 Reg 26, Sel 0 411 // This is implementation dependent, not defined by the ISA 412 413 // CacheErr Register - CP0 Reg 27, Sel 0 414 // NOTE: Page 65 of the ARM, Volume-III indicates that there are four sel. values (0-3) 415 // used by the CacheErr registers. However, on page 134, only one sel value is shown 416 const unsigned Cache_Err_ER = 31; 417 const unsigned Cache_Err_EC = 30; 418 const unsigned Cache_Err_ED = 29; 419 const unsigned Cache_Err_ET = 28; 420 const unsigned Cache_Err_ES = 27; 421 const unsigned Cache_Err_EE = 26; 422 const unsigned Cache_Err_EB = 25; 423 const unsigned Cache_Err_IMPL_HI = 24; 424 const unsigned Cache_Err_IMPL_LO = 22; 425 const unsigned Cache_Err_Index_HI = 21; 426 const unsigned Cache_Err_Index_LO = 0; 427 428 // TagLo Register - CP0 Reg 28 - Even Selects (0,2) 429 const unsigned TagLo_PTagLo_HI = 31; 430 const unsigned TagLo_PTagLo_LO = 8; 431 const unsigned TagLo_PState_HI = 7; 432 const unsigned TagLo_PState_LO = 6; 433 const unsigned TagLo_L = 5; 434 const unsigned TagLo_IMPL_HI = 4; 435 const unsigned TagLo_IMPL_LO = 3; 436 const unsigned TagLo_P = 0; 437 // undefined bits must be written 0 438 439 440 // DataLo Register - CP0 Reg 28 - Odd Selects (1,3) 441 const unsigned DataLo_HI = 31; 442 const unsigned DataLo_LO = 0; 443 444 // TagHi Register - CP0 Reg 29 - Even Selects (0,2) 445 // Not defined by the architecture 446 447 // DataHi Register - CP0 Reg 29 - Odd Selects (1,3) 448 const unsigned DataHi_HI = 31; 449 const unsigned DataHi_LO = 0; 450 451 452 // ErrorEPC - CP0 Reg 30, Sel 0 453 const unsigned ErrorPC_HI = 31; 454 const unsigned ErrorPC_LO = 0; 455 456 // DESAVE - CP0 Reg 31, Sel 0 457 458 459 460 461 462} // namespace MipsISA 463 464#endif 465